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ADC-16 USER GUIDE
READ:
I"O-INT4 = Interrupt Level Select. Avoid using a level already assigned to another I/O
device. Interrupts are chosen as follows:
BUSY
IRQ
IP1
IPO
INT4
INT2
lNTl
INTO
INT4
INT2
INTl
INTO
INTERRUPT LEVEL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disabled
Disabled
Level 2 (XT,
AT)
Level 3 (XT,
AT)
Level
4
(XT,
AT)
Level 5
(
AT)
Disabled
Level 7 (XT,
AT)
Disabled
Level 9
(AT)
Level 10
(AT)
Level
11 (AT)
Level
12 (AT)
Disabled
Disabled
Level 15
(AT)
NOTE:
INTE,
OPO, and OP1 bits are write only. It would be prudent to keep a variable that
contains the status of these bits. These bits could then be read to determine present
status; they should be updated before they are written to the control register. Also, set
OPO
and OP1 to 0 during initialization, to ensure that the variable reflects the true state of
the bit.
8.6 STATUS REGISTER (BASE ADDRESS +3)
The Status Register is a read-only register that provides information on the operation and
configuration of the A/D in the ADC-16. Writing to the Status Register address clears the ADC-16
interrupt request and provides the means of acknowledging the ADC-16 interrupt and re-enabling
it.
The format is as follows:
Base Address
+3
BIT:
07
D6
D5
D4
D3
D2
D1
DO
BUSY
= A P
BUSY. This bit reflects the state of the 4/D converter. If BUSY
=
1, then
the
A D
is performing a conversion. If BUSY = 0, the
N D
is ready
to
begin an
&D
conversion or to read data.
IRQ
=
Interrupt Request. Generated even if bus interrupts are disabled (INTE bit of the
Control Register
=
0). If this bit equals
1,
the
AD
is finished and data is
ready.
Read
the
Status
Register t o clear the IRQ bit.
8 - 4
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