Input Read Test - Keithley PDISO-8 User Manual

Input Read Test

6-10
16. Again, each bit set to ON in the AIO Panel should output a logic-
high signal at the corresponding I/O terminal, reading typically about
4 volts (minimum of 2.2 volts) at a DMM/DVM. Each bit set to OFF
in the AIO Panel should output a logic-low signal at the correspond-
ing I/O terminal, reading typically about 0 volts (maximum of 0.8
volts) at a DMM/DVM.
The typical values shown are valid for boards with TTL
Note:
compatible outputs. For boards with relay outputs (REL-16, PDISO-8,
and PIO-32) the output will be a relay contact closure. For boards with
open collector outputs (PIO-HV) use a pull up resistor to an appropriate
voltage to detect output state. Refer to the hardware description in this
user's guide for more details on the output's electrical specification.
If the bit patterns set on the AIO Panel do not agree with the
G
logic levels measured at the I/O terminals, the board is not
functioning properly. Stop here, and determine why.
If the bit patterns set on the AIO Panel do agree with the logic
G
levels measured at the I/O terminals, and you have performed an
output set test for all ports, the board is functioning properly.
17. Repeat steps 13, 14, and 15 for additional output channels.
A similar test of input circuitry can be performed by applying an input
signal of suitable type to each input line and verifying that the appropriate
input indicator changes state. Refer to the hardware description in this
user's guide for more details on the input's electrical specifications.
Troubleshooting