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12. Each bit set to ON in the AIO Panel should output a logic-high signal
at the corresponding I/O terminal, reading typically about 4 volts
(minimum of 2.2 volts) at a DMM/DVM. Each bit set to OFF in the
AIO Panel should output a logic-low signal at the corresponding I/O
terminal, reading typically about 0 volts (maximum of 0.8 volts) at a
DMM/DVM. Do one of the following:
Note:
compatible outputs. For boards with relay outputs (REL-16, PDISO-8,
and PIO-32) the output will be a relay contact closure. For boards with
open collector outputs (PIO-HV) use a pull up resistor to an appropriate
voltage to detect output state. Refer to the hardware description in this
user's guide for more details on the output's electrical specification.
G
G
13. In the Digital Output Panel under Channels, click on the output
channel to test (channel 0 in this example) as shown in Figure 6-8.
KEITHLEY
Channels
0
1
2
3
8
9
10
11
Figure 6-8. Configuring channel 0 for output bit pattern B
14. In the Digital Output Panel under Output Bits, set the bits of
channel 0 for bit pattern B as shown in Figure 6-8.
15. Measure the voltage between signal ground and each bit of the output
port with a DMM or DVM. Make measurements at the STA-50
terminals or the cabled mating connector that is connected to the
selected CONN-3160-D1 50-pin connector.
The typical values shown are valid for boards with TTL
If the bit patterns set on the AIO Panel do not agree with the
logic levels measured at the I/O terminals, the board is not
functioning properly. Stop here, and determine why.
If the bit patterns set on the AIO Panel agree with the logic levels
measured at the I/O terminals, then repeat steps 9, 10, and 11 for
remaining output channels.
4
5
6
7
12
13
14
15
Output Bits
7
6
5
AA
Digital Output Panel
4
3
2
1
0
6-9
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