Circuit Diagram (Main Pcb Assy/Fdc & Ide Contr. Block) - Roland Va-7 Service Notes

A[0..3]
D[0..15]
5VD
C120
100nFs
C119
100nFs IC16
HD63266-FP-64A
XFDCRST
D
XRD
XWRL
XFDC
XFDCINT
XDREQ1
XDACK1
A1 9 38
XFDCDEND RS1 NC
A0 8 43
FDCCONT RS0 NC
XIDXINT
RDYCNTL R71
63
MON3
62 10Ks
MON2
61
MON1
D7 19
D7
D6 18
D6
5VD D5 17 58 XDS3
D5 DS3
D4 16 57
D4 DS2
D3 15 56
D3 DS1
R68 D2 14
D2
10Ks D1 13
D1
D0 12 52
D0 HLOAD
XFDCRST 3
RESET
C121 XRD 4 30 XINP
E,RD INP
10nFs XWRL 5 34 XINDEX
R/W,WR INDEX
XFDC 6 55 XDS0
D
CS DS0
XDACK1 XFDCINT 21
IRQ
60
MON0
R67 XDREQ1 20 51 XHDIR
DREQ HDIR
7 50 XSTEP
DACK STEP
XFDCDEND 22 48 XWDATA
DEND WDATA
0s 47 XWGATE
C141 WGATE
33 XTRK0
TRK0
39 32 XWPRT
XTAL1 WPRT
TP14 35 XRDATA
RDATA
X2 53 XHSEL
10pFs
HSEL
16MHz 31 XREADY
C142 READY
niu
40
EXTAL1
24
1/2EX1
36
D 10pFs
XTAL2
37
EXTAL2
FDCCONT 1
8"/5"
2
XTALSEL
28
IFS
26
NUM1
27
NUM2
D
IC23C IC23B
XIDXINT 2 6 5 3
TC7W14F TC7W14F
1
RDYCNTL 2
TP9
TP
XIDEINT niu
D
XIDE
XRST
GWAITIN
A18
20MHz
5VD
R73 NIU R80 10Ks
XREADY FDS3
R74 1Ks
R81 10Ks
XRDATA FDS2
R75 1Ks R82
10Ks
XWPRT FDS1
R79 1Ks R83 10Ks
XTRK0 FDS0
R78 1Ks
XINDEX
TO FDD UNIT PC/AT
R77 1Ks
XINP
5VD
C124
XINP
NIU
5VD 5VD
R76
C123 C125
5VD XINDEX 10Ks
100nFs NIU
R69
10Ks
C126
FDS1
NIU
XINP 2
D
4
1 FDS3 6
4 XINDEX 8
2 FDS0 10
C128
IC15 XHDIR FDS1 12
NIU
TC7S08F FDS2 14
16
C129
XSTEP XHDIR 18
NIU
XSTEP 20
D
FDS1 XWDATA 22
XWGATE 24
XTRK0 26
XWPRT 28
C134
XWDATA XRDATA 30
47pFs
XHSEL 32
34
C135
XWGATE
47pFs
C130
XTRK0
NIU
C131
XWPRT
NIU
C132
XRDATA
NIU
C133
XHSEL
NIU
D
C122
5VD
100nFs
D
4 XREADY
IC14
TC7S32F
D
ADDRESS BUS
DATA BUS
IC31
D0 2
A1
D1 3
A2
D2 4
A3
D3 5
A4
D4 6
A5
D5 7
A6
D6 8
A7
D7 9
A8
19
G
1
CN17
DIR
1
3
5
7 74VHC245F
9
11
13
15
17
19
21
23
25
27 IC32
29 D8 2
A1
31 D9 3
A2
33 D10 4
A3
D11 5
A4
D12 6
A5
D13 7
A6
D14 8
D
A7
D15 9
A8
XIDE XIDE 19
G
1
DIR
5VD
R168
RA42 74VHC245F
5VD 8x1Ks 10Ks
1
R169 33s
IC33 R170 100s
31 R171 100s
XRST_OUT
A1 6 40 R172 120s
ADDIN0 ADDOUT0
A2 5 39 R173 120s
ADDIN1 ADDOUT1
A3 4 37 R174 120s
ADDIN2 ADDOUT2
R175 100s
36 R176 100s
BUFF_DIR
25
IDECS0
41
IDECS1
A18 11
A18
29
XIDEINT
XRD 12 9
RDIN IDEINT
XWRL 16 28
WRIN WROUT
27
RDOUT
XIDE 17
CSIDE
26
GWAITOUT
8
IDEIORDY
7
NC
13
NC
18
NC
19 35
NC VCC
20 23
NC VCC
21 15
NC VCC
24 3
NC VCC
32
NC
33 44
NC GND
34 42
NC GND
38 30 C159 C182 C181 C183
NC GND
22 100nFs 100nFs 100nFs 100nFs
GND
20MHz 43 10
CLK GND
2
GND
XRST 14 1
RESETN GND
IDE-7032LC44-15
D
70ns 250ns
30ns 165ns
add
wrl/xrd
wait states =(3+1)*50ns + 1 cycle = 250ns
RA36
5VD 8x1Ks
1 RA38
4x33s
RA37 IDE[0..15]
4x33s
18 1 8 IDE8
B1
17 2 7 IDE9
B2
16 3 6 IDE10 5VD
B3
15 4 5 IDE11 IDEXRST
B4
14 1 8 IDE12 IDE7
B5
13 2 7 IDE13 IDE6
B6
12 3 6 IDE14 R183 IDE5
B7
11 4 5 IDE15 10Ks IDE4
B8
FL7 5VD IDE3
ELKS471FA IDE2
20 1 3 IDE1
VCC
C179 IDE0
100nFs
10
GND
IDEXWRL
IDEXRD
D D
RA39 IDEIORDY
5VD 8x1Ks RA41
4x33s IDEINT
1 IDEA2
RA40 IDEA1
4x33s IDECS0
18 1 8 IDE0
B1
17 2 7 IDE1
B2
16 3 6 IDE2
B3
15 4 5 IDE3
B4
14 1 8 IDE4
B5
13 2 7 IDE5 R142
B6
12 3 6 IDE6
B7
11 4 5 IDE7
B8
FL8 5VD 0s
ELKS471FA NIU
20 1 3
VCC
10
GND
C180
D
100nFs
IDEXRST
IDEXWRL
IDEXRD
IDEA1
IDEA2
IDEA3
IDECS0
IDECS1
C207 C208 C209 C210 C211 C212 C213 C214
D
47pFs 47pFs 47pFs 47pFs 47pFs 47pFs 47pFs 47pFs
NIU NIU NIU NIU NIU NIU NIU NIU
XIDEINT
R145
GWAITIN 22Ks
5VD
D
FL10
ELKS471FA
1 3
C215
100uF16s
IDE
TP17
TP
niu
D
TP18
TP
niu
D
CN22
1 2
3 4 IDE8
5 6 IDE9
7 8 IDE10
9 10 IDE11
11 12 IDE12
13 14 IDE13
15 16 IDE14
17 18 IDE15
19 20
21 22
23 24
25 26 TO ZIP IDE
27 28
29 30
31 32
33 34
35 36 IDEA3
37 38 IDECS1
39 40
R141 5VD
D
22Ks
R143
22Ks
5VD
IC23D
C127
100nFs
TC7W14F
D
IC23A
1 7
TC7W14F
D