Evaluation Board Schematics And Artwork - Analog Devices EVAL-SSM3582Z User Manual

UG-934

EVALUATION BOARD SCHEMATICS AND ARTWORK

I 2 S_ I 2 C
ADDR1
ADDR0
SCL_ 3 5 8 2
SDA_ 3 5 8 2
OMCK_ I N FSYNC_ 3 5 8 2
SDATA_ 3 5 8 2
BCLK_ 3 5 8 2
8 4 1 6 _ MCLK
SHEET-3
POWER_SUPPLY
PV D D I N PU T PVDD
+ 5 V_ EXT
E X T S U PPLY
+ 3 V3 _ EXT
+ 1 V8 _ EXT
SHEET- 4
PV D D
LDO_ 5 V_ EN
TP1
TP2
TP3
SCL_ 3 5 8 2
TP4
SDA_ 3 5 8 2
TP5
FSYNC_ 3 5 8 2 TP6
SDATA_ 3 5 8 2 TP7
BCLK_ 3 5 8 2 TP8
TP9
TP1 0
T O S S M 3 5 8 2
+ 5 V
T O S PD I F R X
+ 3 V3
+ 1 V8
T O S S M 3 5 8 2
Figure 6. Schematic of the
C1 4
0 .2 2 µ F
1
PGND
2
PGND
3
AVDD_EN
SCL_ 3 5 8 2 4
SCL
5
S D A_ 3 5 8 2
SDA
6
FS YN C_ 3 5 8 2
FSYNC
7
S D ATA_ 3 5 8 2
SDATA
8
BCLK_ 3 5 8 2
BCLK
9
PGND
1 0
PGND
C4 3 C4 4 C4 5
1 0 pF 1 0 pF 1 0 pF
C3 1
0 .2 2 µ F
Figure 7. Schematic of the
SSM3 5 8 2
SHEET- 2
SSM3582 Evaluation Board Block Diagram
PVDD
PVDD
C1 5 C1 3
0 . 1 0 µ F 1 0 µ F
C1 6
0 .2 2 µ F
U5
3 0
GND
PGND
2 9
GND
PGND
2 8
DVDD_ 3 5 8 2
DVDD
2 7
ADDR1
ADDR1
2 6
ADDR0
ADDR0
2 5
GND
AGND
2 4 AVDD_ 3 5 8 2
AVDD
2 3 LDO_ 1 V8 _ EN
DVDD_EN
2 2
GND
PGND
2 1
GND
PGND
SSM3 5 8 2
C3 3
PVDD
0 .2 2 µ F
C3 2 C3 7
1 0 µ F
0 . 1 0 µ F
PVDD
SSM3582 Evaluation Board, SSM3582
Rev. 0 | Page 6 of 13
EVAL-SSM3582Z User Guide
ADDR1 OUTL+
ADDR0 OUTL–
OUTR+
OUTR–
SCL_ 3 5 8 2
SDA_ 3 5 8 2
FSYNC_ 3 5 8 2
SDATA_ 3 5 8 2
BCLK_ 3 5 8 2
+ 1 V8
1
2
J1 7
C1 9
C1 7
0 . 1 0 µ F
1 0 µ F
AV D D _ 3 5 8 2
TP3 0
TP2 9
TP2 8
AD D R1
TP2 7
TP2 5 AD D R0
TP2 6
1
TP2 4
TP2 3
TP2 2 2 - JUMPER
TP2 1
AVDD_ 3 5 8 2
C 2 6 C2 9
0 . 1 0 µ F 1 0 µ F
Section
OUTPUTS
OUTL+
OUTL-
OUTR+
OUTR–
SHEET- 5
AV D D _ 3 5 8 2
+5V
J2 3
2