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Portwell NAR-5050-310 User Manual

Nar-5050 series, communication appliance
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NAR-5050 Series
Communication Appliance
User s Manual
Revision: 010
Portwell Inc.
3F, No. 92, Sec. 1, Nei-Hu Rd., Taipei 114, Taiwan, R.O.C.
Headquarter: +886-2-2799-2020
FAX: +886-2-2799-1010
http://www.portwell.com.tw
Email: info@mail.portwell.com.tw

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Summary of Contents for Portwell NAR-5050-310

  • Page 1 NAR-5050 Series Communication Appliance User s Manual Revision: 010 Portwell Inc. 3F, No. 92, Sec. 1, Nei-Hu Rd., Taipei 114, Taiwan, R.O.C. Headquarter: +886-2-2799-2020 FAX: +886-2-2799-1010 http://www.portwell.com.tw Email: info@mail.portwell.com.tw...

  • Page 2: Table Of Contents

    Item NO: B8980690 Table of Contents Chapter 1 Introduction .........................2 About This Manual....................2 Manual Organization....................2 Technical Support Information ................2 Chapter 2 Getting Started ......................3 Included Hardware....................3 Before You Begin....................3 The Chassis......................4 Open the Chassis ....................4 Remove and Install DIMM..................5 Remove and Install DOM..................5 Remove and Install Battery..................6 Install HDD ......................7 Remove and Install PCI card .................9...

  • Page 3: Chapter 1 Introduction

    1.3 Technical Support Information Users may find helpful tips or related information on Portwell's web site: http://www.portwell.com.tw. A direct contact to Portwell's technical person is also available. For further support, users may also contact Portwell’ s headquarter in Taipei or local distributors.

  • Page 4: Chapter 2 Getting Started

    Taipei Office Phone Number: +886-2-27992020 Chapter 2 Getting Started This section describes how the hardware installation and system settings should be done. 2.1 Included Hardware The following hardware is included in package: PPAP-3710L-0200 Communication Appliance System Board  One null serial port cable ...

  • Page 5: The Chassis

    The system is integrated in a customized 1U chassis (Fig. 2-1, Fig. 2-2). On the front panel you will find a 4-push-button LCD module (EZIO), three or five LAN ports and a COM port. NAR-5050-310 NAR-5050-510 Fig. 2-1 Front view of the chassis Fig.

  • Page 6: Remove And Install Dimm

    1. Loosen the six screws of the chassis, two on each side and the rest two on the back , remove lead (Fig. 2-3). Fig. 2-3 Take off screws 2. The top lead (Fig. 2-4) can be removed from the base stand (Fig. 2-5). Fig.

  • Page 7: Remove And Install Battery

    Fig. 2-8 Compact Flash Card Fig. 2-9 Insert Compact Flash Card into the CF interface 2. The completed installation of Compact Flash Card is shown as Fig. 2-10. Fig. 2-10 Completion of Compact Flash Card connection 2.7 Remove and Install Battery 1.

  • Page 8: Install Hdd

    2.8 Install HDD The system has an internal drive bay for one 2.5" hard disk drive. If the HDD is not pre-installed, you can install it by yourself. Follow the steps below to install the HDD: 1. Fasten the four screws to lock HDD and bracket together (Fig. 2-13a, 2-13b). Fig.
  • Page 9 2.9 Remove and Install PCI card One PCI slot is available to NAR-5050 series. Follow the steps below for installation: 1. Loosen the screws (on the top lead) and remove the top lead (Fig. 2-17). 2. Remove the screw on the side (Fig. 2-18). Fig.

  • Page 10: Remove And Install Pci Card

    lead 2.10 Remove and Install PCI-X card One PCI-X slot is available to NAR-5050 series. Follow the steps below for installation: 6. Loosen the screws (on the top lead) and remove the top lead (Fig. 2-22). Push the PCI-X add-on card into the PCI-X slot (Fig. 2-23). Fig.

  • Page 11: Product Specifications

    One 2.5” hard disk bay for DMA/33/66/100 IDE hard disk  Serial Ports: Support two high-speed 16550C compatible UARTs with 16-byte T/R FIFOs  (Optional) Support LCD/Key pad module (Portwell proprietary)  USB Interface: Support two USB1.0 ports for high speed I/O peripheral devices  Auxiliary I/O Interfaces: System reset switch, power okay LED and HDD LED interface ...

  • Page 12: Hardware Configuration Setting

    2.11 Hardware Configuration Setting This section gives the definitions and shows the positions of jumpers, headers and connectors. All of the configuration jumpers on PPAP-3710L-0200 are in the proper position. The default settings set by factory are marked with a star ( ★ ). Jumpers In general, jumpers on PPAP-3710L-0200 system board are used to select options for certain features.
  • Page 13 Figure 2-22 PPAP-3710L-0200 Jumper Table NAR-5050/5070 Series User’ s Manual...
  • Page 14 Connector Connector Function LAN#1 Gbit (BUS#0,DEVSEL#2) AUX 5V OUT GPIO ATX POWER CONNECTOR POWER(GREEN) & IDE(ORANGE) LED CPU FAN SYSTEM FAN#1 SYSTEM FAN#2 SYSTEM FAN#3 SYSTEM FAN#4 FORNT PANEL FAN PS2 KEYBOARD/MOUSE COM2 COM1 PCI32 PCI-X DIMM#1 DIMM#2 LAN#2 LAN#3 IDE CNANNEL0 (44pin) IDE CHANNEL1 CF CARD CHASSIS INTRUSION...

  • Page 15: Install A Different Processor

    2.12 Install a Different Processor Install CPU 1. Lift the handling lever of CPU socket outwards and upwards to the other end. 2. Align the processor pins with holes on the socket. Make sure that the notched corner or dot mark (pin 1) of the CPU corresponds to the socket's bevel end.
  • Page 16 2. Enter a name to create new dial 3. For the connection settings, make it Direct to Com1. 4. Please make the port settings to Baud rate 19200, Parity None, Data bits 8, Stop bits 1 5. Turn on the power of NAR-5050 series, after following screen was shown: NAR-5050/5070 Series User’...

  • Page 17: Bios Setup Information

    6. You can then see the boot up information of NAR-5050 series. 7. When message “ Hit <DEL> if you want to run Setup” appear during POST, after turning on or rebooting the computer, press <Tab> key immediately to enter BIOS setup program. This is the end of this section.
  • Page 18 Entering Setup When message “ Hit <DEL> if you want to run Setup” appear during POST, after turning on or rebooting the computer, press <Del> key immediately to enter BIOS setup program. To enter Setup but fail to respond before the message disappears, please restart the system either by first turning it off and followed by turning it on (COLD START) or simply press the "RESET"...
  • Page 19 Standard CMOS Features Frequency /Voltage Control Advanced BIOS Features Load Fail/Safe Defaults Advanced Chipset Features Load Optimized Defaults Integrated Peripherals Set Supervisor Password Power Management Setup Set User Password PnP/PCI Configurations Save & Exit Setup PC Health Status Exit Without Saving ...

  • Page 20: Bios Features Setup

    80MONO All Errors No Errors Select the situation in which you want the BIOS Halt On All, but Keyboard to stop the POST process and notify you All, but Diskette All, but Disk/Key Display the amount of conventional memory Base Memory detected during boot up Display the amount of extended memory Extended Memory...
  • Page 21 Set the RS-232 baud rate speed. The choice: 9600, 19200, 38400, 57600 and 115200. Cache Setup CPU L1 & L2 Cache ( Enabled or Disabled CPU L1 and L2 cache ) Enabled Enable cache Disabled Disable cache CPU L2 Cache ECC Checking ( Enabled or Disabled CPU L2 cache ECC checking ) Enabled Enable checking Disabled...
  • Page 22 The choice: Enabled/Disabled. Typematic Rate Setting Keystrokes repeat at a rate determined by the keyboard controller. When enabled, the typematic rate and typematic delay can be selected. The choice: Enabled/Disabled. Typematic Rate (Chars/Sec) Set the how many number of times a second to repeat a keystroke when you hold the key down.

  • Page 23: Reset To Default Information

    2.15 Reset to Default Information This programming guide is for PPAP-3710L-0200 Reset to Default (RST2DFT) feature. Pin51 of NS PC87417, GPIO45, is defined as RST2DFT status pin that can be read out to indicate RST2DFT flag. The RST2DFT flag is defined as following: (1) "1"...
  • Page 24 GPCFG1 db F1h ; Index F1h GPDI4 db 0Bh ; Offset 0Bh push dx push bx push ax ;RD_R2D Step 1: Select multiplex pin,pin51,as GPIO45 Definition ( Clear Index-23h_Bit1 ) mov dx,Index_IO_Port ; Read SIOCFG3 First mov al,SIOCFG3 out dx,al mov dx,Data_IO_Port in al,dx and al,0fdh...
  • Page 25 mov al,45h out dx,al ;RD_R2D Step 4 :Define GPIO45 as an input pin with internal Pull high ;( GPCFG1_P46h ) mov dx,Index_IO_Port mov al,GPCFG1 out dx,al mov dx,Data_IO_Port mov al,46h out dx,al ;RD_R2D Step 5 : Read GPIO I/O Base Address ;( Index-60h contains A15---A8, Index-61h contains A7---A0 ) mov dx,Index_IO_Port ;...

  • Page 26: Wdt Information

    Folloing code segment is for reference only. Example of RST2DFT application SET_RST2DFT DW 0CDEFh ; Declare the I/O port Polling_RST2DFT : Call RST2DFT_Flag_Read ; read RST2DFT flag. jnc LOAD_DEFAULT ; Flag is "0" ,then jump to ; LOAD_DEFAULT State NORMAL_STATE : ;...
  • Page 27 ; Input : DH ; Twd , the Time-out period 0 --> 255 Minutes, ; Return : None WDT Enable PROC near push dx push ax push cx push bx mov ch,dh ; Save dh, Twd , value in ch ;...
  • Page 28 ; Enable WDT Step 3 : Read SWC I/O Base Address ; ( Index-60h contains A15---A8, Index-61h contains A7---A0 ) mov dx,Index_IO_Port ; Read Index 60h mov al,60h out dx,al mov dx,Data_IO_Port in al,dx mov bh,al ; High Byte I/O Base Addr --> BH mov dx,Index_IO_Port mov al,61h ;...
  • Page 29 sub dx,bx ; dx back to I/O base Addr. ; Enable WDT Step 7 : Enable SW_WD_TREN ( Offset-12h_Bit7P1 ) ; Allow S/W to trigger WDT xor bx,bx mov bl,WDCFG add dx,bx ; Point to WDCFG offset in al,dx ; Read this I/O port value first or al,80h ;...
  • Page 30 push dx push ax push cx push bx mov ch,dh ; Save dh, Twd , value in ch ;Refresh WDT Step 1: Select multiplex pin,pin55,as WDT output (Set Index-22h_Bit7) mov dx,Index_IO_Port ; Read SIOCFG2 First mov al,SIOCFG2 out dx,al mov dx,Data_IO_Port in al,dx or al,80h ;...
  • Page 31 out dx,al mov dx,Data_IO_Port in al,dx mov bh,al ; High Byte I/O Base Addr --> BH mov dx,Index_IO_Port mov al,61h ; Read Index 60h out dx,al mov dx,Data_IO_Port in al,dx mov bl,al ; High Byte I/O Base Addr --> BL mov dx,bx ;...
  • Page 32 mov al,ch ; Write the Twd value in minutes out dx,al sub dx,bx ; dx back to I/O base Addr. ;Refresh WDT Step 8 : Enable WDEN ( Offset-10h_Bit0P1 ) ;Enable WDT Function, Once set, can not be cleared except reset xor bx,bx mov bl,WDCTL add dx,bx...
  • Page 33 ; Data_IO_Port dw 002Fh ; SWC_LDN db 04h ; SIOCFG2 db 22h ; WDCTL db 10h ; WDTO db 11h ; WDCFG db 12h ; Input : None ; Return : None WDT disable PROC near push dx push ax push bx ;Disable WDT Step 1: Select multiplex pin,pin55,as WDT output (Set Index-22h_Bit7) mov dx,Index_IO_Port...
  • Page 34 ;Disable WDT Step 3 : Read SWC I/O Base Address ;( Index-60h contains A15---A8, Index-61h contains A7---A0 ) mov dx,Index_IO_Port ; Read Index 60h mov al,60h out dx,al mov dx,Data_IO_Port in al,dx mov bh,al ; High Byte I/O Base Addr --> BH mov dx,Index_IO_Port mov al,61h ;...

  • Page 35: Gpio Information

    ;Disable WDT Step 7 : Program WDTO,Twd, to "00h". ( Offset-11h_P00h ) ;Write Twd "00h" to stop WDT counting xor bx,bx mov bl,WDTO add dx,bx ; Point to WDTO offset mov al,00h ; Write the Twd 00h out dx,al sub dx,bx ;...
  • Page 36 GET_GPI_STATUS_CH PROC NEAR push edx push ebx push ax xor ch,ch ; init ch = 0 ;Get_GPI Step 1 : Enable GPIO function ( Set GPIO_Index-30h_Bit0 ) mov dx,Index_IO_Port ; Point to GPIO_LDN ( LDN = 7 ) mov al,07 out dx,al mov dx,Data_IO_Port mov al,GPIO_LDN...
  • Page 37 ;Get_GPI Step 3 : Get GPI_Bits ; Bit7 of Ch start ------------------------------ ; GPIO30 : JP1 of test module ; EBX_Bit[31..24] : GPDI3 = 09h, ; EBX_Bit[23..16] : MASK bit ( which bit ) , GPIO30 --> 00h ; EBX_Bit[15..8] : GPCFG1(LDN07_Index_F1h) Data = ( read value ) or 06h ;...
  • Page 38 ror ebx,10h ; Swap EBX high and low word mov bl,07h ; EBX_Bit[23..16] mov bh,GPDI3 ; EBX_Bit[31..24] rol ebx,10h ; Restore the Swap of EBX high and low word call LOOP_GET_GPI_CARRY ; call get GPDI jc set_bit6 ; if carry , then Bit6=1 and ch,0Bfh ;...
  • Page 39 ; Bit4 of Ch start ------------------------------ ; GPIO36 : JP4 of test module ; EBX_Bit[31..24] : GPDI3 = 09h, ; EBX_Bit[23..16] : MASK bit ( which bit ) , GPIO26 --> 06h ; EBX_Bit[15..8] : GPCFG1(LDN07_Index_F1h) Data = ( read value ) or 06h ;...
  • Page 40 ror ebx,10h ; Swap EBX high and low word mov bl,02h ; EBX_Bit[23..16] mov bh,GPDI3 ; EBX_Bit[31..24] rol ebx,10h ; Restore the Swap of EBX high and low word call LOOP_GET_GPI_CARRY ; call get GPDI jc set_bit3 ; if carry , then Bit3=1 and ch,0F7h ;...
  • Page 41 ; Bit1 of Ch start ------------------------------ ; GPIO33 : JP7 of test module ; EBX_Bit[31..24] : GPDI3 = 09h, ; EBX_Bit[23..16] : MASK bit ( which bit ) , GPIO33 --> 03h ; EBX_Bit[15..8] : GPCFG1(LDN07_Index_F1h) Data = ( read value ) or 06h ;...
  • Page 42 mov bh,al ; EBX_Bit[15..8] ror ebx,10h ; Swap EBX high and low word mov bl,04h ; EBX_Bit[23..16] mov bh,GPDI3 ; EBX_Bit[31..24] rol ebx,10h ; Restore the Swap of EBX high and low word call LOOP_GET_GPI_CARRY ; call get GPDI jc set_bit0 ; if carry , then Bit0=1 and ch,0FEh ;...
  • Page 43 LOOP_GET_GPI_CARRY PROC NEAR mov dx,Index_IO_Port ; Program GPSEL first ( port# and Pin# ) mov al,GPSEL out dx,al mov dx,Data_IO_Port mov al,bl out dx,al mov dx,Index_IO_Port ; Program GPCFG1 ( port dir. type,..) mov al,GPCFG1 out dx,al mov dx,Data_IO_Port mov al,bh out dx,al ror ebx,10h ;...
  • Page 44 ; GPCFG1 : Index 0F1h from GPIO LDN ; Set GPIO direction, type, ; GPDO3 : Offset from I/O base Addr. for GPIO = 08h ; GPDI3 : Offset from I/O base Addr. for GPIO = 09h ; Input : DH : bit 7 : GPO30 : PPAP-LED2 D16 6 : GPO37 : PPAP-LED2 D15 5 : GPO31 : PPAP-LED2 D14 4 : GPO36 : PPAP-LED2 D13...
  • Page 45 out dx,al mov dx,Data_IO_Port in al,dx mov bh,al ; High Byte I/O Base Addr --> BH mov dx,Index_IO_Port mov al,61h ; Read Index 61h out dx,al mov dx,Data_IO_Port in al,dx mov bl,al ; High Byte I/O Base Addr --> BL mov dx,bx ;...
  • Page 46 mov bl,37h ; EBX_Bit[7..0] = 37h mov dx,Index_IO_Port ; Read Index F1h first mov al,GPCFG1 out dx,al mov dx,Data_IO_Port in al,dx or al,07h ; OR 07h mov bh,al ; EBX_Bit[15..8] ror ebx,10h ; Swap EBX high and low word mov bl,ch and bl,40h ;...
  • Page 47 and bl,20h ; Other bits = 0 except Bit5 ror bl,04h ; Bit5 rotate to Bit1 for EBX_Bit[23..16] mov bh,bl ; Temperoary save in BH ; Keep bit7,6 start --------------------- mov bl,ch and bl,40h ; Other bits = 0 except Bit6 rol bl,01h ;...
  • Page 48 mov bl,ch and bl,40h ; Other bits = 0 except Bit6 rol bl,01h ; Bit6 rotate to Bit7 for EBX_Bit[23..16] add bh,bl ; Add BIt6 of ch in BH mov bl,ch ; Bit7 of Ch needs to be saved since Programmed and bl,80h ;...
  • Page 49 mov bl,ch and bl,20h ; Other bits = 0 except Bit5 ror bl,04h ; Bit5 rotate to Bit1 for EBX_Bit[23..16] add bh,bl ; Add BIt5 of ch in BH mov bl,ch and bl,40h ; Other bits = 0 except Bit6 rol bl,01h ;...
  • Page 50 and bl,08h ; Other bits = 0 except Bit3 ror bl,01h ; Bit3 rotate to Bit2 for EBX_Bit[23..16] add bh,bl ; Add Bit3 of ch in BH mov bl,ch and bl,10h ; Other bits = 0 except Bit4 rol bl,02h ;...
  • Page 51 and bl,02h ; Other bits = 0 except Bit1 rol bl,02h ; Bit1 rotate to Bit3 for EBX_Bit[23..16] mov bh,bl ; Temperoary save in BH ; Keep bit7,6,5,4,3,2 start --------------------- mov bl,ch and bl,04h ; Other bits = 0 except Bit2 rol bl,03h ;...
  • Page 52 mov bl,34h ; EBX_Bit[7..0] = 34h mov dx,Index_IO_Port ; Read Index F1h first mov al,GPCFG1 out dx,al mov dx,Data_IO_Port in al,dx or al,07h ; OR 07h mov bh,al ; EBX_Bit[15..8] ror ebx,10h ; Swap EBX high and low word mov bl,ch and bl,01h ;...
  • Page 53 mov bh,GPDO3 ; EBX_Bit[31..24] rol ebx,10h ; Restore the Swap of EBX high and low word call LOOP_GPO_BITS ; call output GPDO ; Bit0 of Ch end --------------------------------- pop cx pop ax pop ebx pop edx GPO_OUT_BYTE_DH ENDP ;-----------------------------------------------------------------------; LOOP_GPO_BITS ;-----------------------------------------------------------------------;...
  • Page 54 ror ebx,10h ; Swap EBX High and low word ror edx,10h ; Get GPIO I/O Base Addr to DX. xor ax,ax mov al,bh ; Get Offset Addr value add dx,ax ; Point to Offset Addr. mov al,bl ; Get GPDO data out dx,al ;...
  • Page 55 pop dx FIXDELAY ENDP ;---------------------------------------------------------------; LOOP_DISPLAY_4_CHAR ;---------------------------------------------------------------; Input : NONE STACK PRESENT Output: NONE ;---------------------------------------------------------------; LOOP_DISPLAY_4_CHAR PROC NEAR push ax push cx push dx mov cx,01800h ; loop count for "/|\-" total_count : push cx loop_message : mov cx,03h loop_message_init : cmp cx,03h jne loop_message1 mov ah,02h...
  • Page 56 ; call fixdelay ; pop cx jmp loop_message_init loop_message2 : cmp cx,01h jne loop_message3 mov ah,02h mov dl,5Ch ; cx = 1 , "X" display int 21h dec cx lea dx,promp_bs ; back space , ASCII="08h" mov ah,9 int 21h push cx mov cx,0010h call fixdelay...

  • Page 57: Chapter 3 Operation Guide

    Chapter 3 Operation Guide 3.1 Brief Guide of PPAP-3710L-0200 PPAP-3710L-0200 is a Communication Appliance computing board based on Server Works CMIC-SL chipset technology. PPAP-3710L-0200 has three on-board LAN ports to serve communication appliances, such as Firewall, which needs three Ethernet ports to connect external network (internet), demilitarized zone and internal network.

  • Page 58: System Architecture

    3.2 System Architecture The following illustration of block diagram illustrated basic design reference of PPAP-3710L- 0200, a highly integrated system solution. The most up-to-date system architecture of PPAP- 3710L-0200 includes two main VLSI chips. It contains CMIC-SL and CSB5 to support mPGA Celeron/Pentium 4 processor, DIMM, PCI bus interface, USB port, SMBus communication, and Ultra DMA/100 IDE Master.

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