Samsung SC32442B54 User Manual page 488

SC32442B RISC MICROPROCESSOR
TIMING DIAGRAM
CAMVSYNC
CAMHREF
CAMHREF
(1H)
CAMPCLK
CAMDATA
[7:0]
CAMPCLK
CAMDATA
[7:0]
There are two timing reference signals in ITU-R BT 656 format, one is at the beginning of each video data block
(start of active video, SAV) and other is at the end of each video data block (end of active video, EAV) as shown
in Figure 23-3 and Table 23-2.
Y Cb Y Cr
Figure 23-2 ITU-R BT 601 Input Timing Diagram
FF 00 00 XY
Video timing
reference codes
Figure 23-3 ITU-R BT 656 Input Timing Diagram
1 frame
Vertical lines
Horizontal width
8-bit mode
Y Cb Y
Y Cb Cr
Pixel data
CAMERA INTERFACE
Cb Y Cr
FF 00 00 XY
Video timing
reference codes
23-3