Teac DV-H500 Service Manual page 22

4. IC22, IC23 (KM416S1120D
PIN DESCRIPTION
Pin Name
CLK System Clock
CS Chip Select
CKE Clock Enable
A ~ A /AP Address
0 10
BA Bank Select Address
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
L(U)DQM Data Input/Output Mask
DQ ~ Data Input/Output
0 15
V /V Power Supply/Ground
DD SS
V /V Data Output Power/Ground
DDQ SSQ
No Connection/
N.C/RFU
Reserved for Future Use
16M SDRAM)
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA ~ RA , column address : CA
0 10
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t after the clock and masks the output.
SHZ
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
2-22
Input Function
~ CA
0 7