Chelsio Communications T4 Installation And User Manual page 30

Unified wire for windows
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Chapter I. Chelsio Unified Wire
SOP
1fe
EOP
1fe
MOD |<-core<----PCIE<----SGE<------UTX<----|
SOP |
3fc
EOP |
?
MOD |->core-->PCIE-->SGE-->UTX---->TPC------->TPE---->MPS---->XGMAC--->wire
SOP
3fc
EOP
3fc
DROP: ???
???
*************************INGRESS (RX) PATH *********************************
MOD
core<-PCIE<---SGE<--CSW<-----TPC<-URX<--TPE<-----MPS<----XGMAC<---wire
SOP
3fc
EOP
3fc
DROP: ???
???
INTS:
f<-
e
stats
Description: Prints MAC statistics for a given port or TP MIB statistics.
Syntax: cxgbtool [vbdInterface] stats [mac{portInstance}|mib]
Example:
C:\Users\Administrator>cxgbtool vbd0 stats mac0
LOW
0x00000000
HIGH
0x00000066
LOW
0x0003f000
HIGH
0x00aa00ee
LOW
0x00000000
HIGH
0x0000eeee
LOW
0x00000000
HIGH
0x0000eeee
LOW
0x00000000
HIGH
0x00000000
LOW
0x0070000b
HIGH
0x0000eeee
LOW
0x00000013
HIGH
0x0000eeee
LOW
0x00000013
HIGH
0x001199cc
LOW
0x00000016
HIGH
0x00020491
LOW
0x0000000b
HIGH
0x00cc0022
LOW
0x00c0000a
HIGH
0x00000000
LOW
0x0000000a
Chelsio T5/T4 Unified Wire for Windows
a
0
a
0
2
1c
2
1c
1c
1c
19 (19) 19
1c
1c
19 (19) 19
???
???
1c
6
5
1c
6
5
???
f<-
6
f<-
|
|
#Request DATA
ff
12 (182) 182
ff
12 (182) 182
0
0
19
2
2
2
19
2
2
2
0(mib)
0(err)
0(oflow) f8(cls)
0
f<-
0 (PCIE<-SGE, channels 0 to 3)
3fc
fffffffc
3fc
fffffffc
???
92
92
3fc
fffffc
92
92
3fc
30

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