Yamaha YSP-4300 Service Manual page 92

YSP-CU4300/YSP-CU3300/NS-WSW160
Pin
Function Name
No.
G3 RESET
L4 AMUTE0/ RESETOUT
J1 TMS
J2 TDI
J3 TDO
H3 TCK
J4 TRST
J5 EMU[0]/GP7[15]
R12 EMA_CLK/OBSCLK/AHCLKR2/ GP1[15]
F2 OSCIN
F1 OSCOUT
E2 OSCVSS
D1 PLL0_VDDA
E1 PLL0_VSSA
G1 RTC_CVDD
H1 RTC_XI
H2 RTC_XO
G2 RTC_VSS
M16 EMA_D[15]/UHPI_HD[15]/ GP0[15]
N14 EMA_D[14]/UHPI_HD[14]/GP0[14]
N16 EMA_D[13]/UHPI_HD[13]/GP0[13]
P14 EMA_D[12]/UHPI_HD[12]/GP0[12]
P16 EMA_D[11]/UHPI_HD[11]/GP0[11]
R14 EMA_D[10]/UHPI_HD[10]/GP0[10]
T14 EMA_D[9]/UHPI_HD[9]/GP0[9]
N12 EMA_D[8]/UHPI_HD[8]/GP0[8]
M15 EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/
BOOT[13]
N13 EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]
N15 EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]
P13 EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]
P15 EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]
R13 EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]
R15 EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1]
T13 EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/
BOOT[12]
N11 EMA_A[12]/ GP1[12]
P11 EMA_A[11]/ GP1[11]
N8 EMA_A[10]/ GP1[10]
R11 EMA_A[9]/ GP1[9]
T11 EMA_A[8]/ GP1[8]
N10 EMA_A[7]/ GP1[7]
P10 EMA_A[6]/ GP1[6]
R10 EMA_A[5]/ GP1[5]
T10 EMA_A[4]/ GP1[4]
N9 EMA_A[3]/ GP1[3]
P9 EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2]
R9 EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1]
T9 EMA_A[0]/ GP1[0]
P8 EMA_BA[1]/ UHPI_HHWIL/GP1[13]
R8 EMA_BA[0]/ GP1[14]
R12 EMA_CLK/OBSCLK/AHCLKR2/GP1[15]
T12 EMA_SDCKE/GP2[0]
N7 EMA_RAS /EMA_CS[5]/GP2[2]
L16 EMA_CAS /EMA_CS[4]/GP2[1]
N7 EMA_RAS/ EMA_CS[5] /GP2[2]
L16 EMA_CAS/ EMA_CS[4] /GP2[1]
T7 EMA_CS[3] /AMUTE2/GP2[6]
P7 EMA_CS[2] /UHPI_HCS/GP2[5]/BOOT[15]
T8 EMA_CS[0] /UHPI_HAS/GP2[4]
M13 EMA_WE /UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]
P12 EMA_WE_DQM[1] /UHPI_HDS2/AXR0[14]/GP2[8]
92
TYPE
(1)
Device Reset and JTAG
I
O (3)
I
I
O
I
I
I/O
High-Frequency Oscillator and PLL
O
I
O
GND
PWR
GND
Real-Time Clock and 32-kHz Oscillator
PWR
I
O
GND
External Memory Interface A (ASYNC, SDRAM)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
External Memory Interface A (EMIFA) Terminal Functions (continued)
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
PULL
Detail of Function
(2)
EMIFA Async chip select
IPD Reset output. Multiplexed with McASP0 mute output.
IPU JTAG test mode select
IPU JTAG test data input
IPD JTAG test data output
IPU JTAG test clock
IPD JTAG test reset
IPU Miscellaneous emulation pin.
IPU PLL Observation Clock
Oscillator input
Oscillator output
Oscillator ground (for filter only)
PLL analog VDD (1.2-V filtered supply)
PLL analog VSS (for filter)
RTC module core power ( isolated from rest of chip CVDD)
Low-frequency (32-kHz) oscillator receiver for real-time clock
Low-frequency (32-kHz) oscillator driver for real-time clock
Oscillator ground (for filter)
IPD EMIFA data bus
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU EMIFA address bus
IPU
IPU
IPU
IPU
IPD
IPD
IPD
IPD
IPD
IPU
IPU
IPD
IPU EMIFA bank address
IPU
IPU EMIFA clock
IPU EMIFA SDRAM clock enable
IPU EMIFA SDRAM row address strobe
IPU EMIFA SDRAM column address strobe
IPU EMIFA Async chip select
IPU
IPU
IPU
IPU EMIFA SDRAM chip select
IPU EMIFA SDRAM write enable
IPU EMIFA write enable/data mask for EMA_D[15:8]