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Pin function (2/2)
No.
Pin name
I/O
No Connect
19
NC
-
Analog Input Format Select Pin
20
ADIF
I
"H" : Full-differential input, "L" : Single-ended input
Chip Address 1 Pin
21
CAD1
I
Chip Address 0 Pin
22
CAD0
I
DAC3 Lch Analog Output Pin
23
LOUT3
O
DAC3 Rch Analog Output Pin
24
ROUT3
O
DAC2 Lch Analog Output Pin
25
LOUT2
O
DAC2 Rch Analog Output Pin
26
ROUT2
O
DAC1 Lch Analog Output Pin
27
LOUT1
O
DAC1 Rch Analog Output Pin
28
ROUT1
O
Lch Analog Negative Input Pin
29
LIN-
I
Lch Analog Positive Input Pin
30
LIN+
I
Rch Analog Negative Input Pin
31
RIN-
I
Rch Analog Positive Input Pin
32
RIN+
I
Zero Input Detect 2 Pin (Note 2)
33
DZF2
O
Analog Input Overflow Detect Pin (Note 3)
OVF
O
Common Voltage Output Pin,AVDD/2
34
VCOM
O
Positive Voltage Reference Input Pin,AVDD
35
VREFH
I
Analog Power Supply Pin,4.5V~5.5V
36
AVDD
-
Analog Ground Pin,0V
37
AVSS
-
Zero Input Detect 1 Pin (Note 2)
38
DZF1
O
Master Clock Input Pin
39
MCLK
I
Parallel / Serial Select Pin
40
P/S
I
Audio Data Interface Format 0 Pin in parallel mode
41
DIF0
I
Chip select pin in 3-wire serial control mode
CSN
I
This pin should be connected to DVDD at I2C bus control mode
Audio Data Interface Format 1 Pin in parallel mode
42
DIF1
I
Control Data Clock Pin in serial control mode
SCL/CCLK
I
I2C = "L" : CCLK(3-wire Serial), I2C = "H" : SCL(I2CBus)
Loopback Mode 0 Pin in parallel control mode
43
LOOP0
I
Control Data Input Pin in serial control mode
SAD/CDTI
I/O
Loopback Mode 1 Pin (Note 1)
44
LOOP1
I
Notes : 1. SDOS, SMUTE, DFS, and LOOP1 pins are ORed with register data if P/S = "L".
2. The group 1 and 2 can be selected by DZFM2-0 bit if P/S = "L" and DZFME = "L".
3. This pin becomes OVF pin if OVFE bit is set to "1" at serial control mode.
4. All input pins should not be left floating.
Function
No internal bonding.
When the input data of the group 1 follow total 8192LRCK cycles with "0" input data,
this pin goes to "H".
This pin goes to "H" if the analog input of Lch or Rch is overflows.
Large external capacitor around 2.2uF is used to reduce power-supply noise.
When the input data of the group 1 follow total 8192 LRCK cycles with "0" input data,
this pin goes to "H".
"L" : Serial control mode, "H" : Parallel control mode
Enables digital loop-back from ADC to 3 DACs.
I2C = "L" : CDTI(3-wire Serial), I2C = "H" : SDA(I2CBus)
Enable all 3 DAC channels to be input from SDTII.
RX-7012VSL
AK4527(1/2)
1-11
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