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Parameter
WR#/WRH# low time
(with RW-delay)
WR#/WRH# low time
(no RW-delay)
ALE falling edge to
CS#
RDCS#/WRCS# low
time
(with RW-delay)
RDCS#/WRCS# low
time
(with RW-delay)
Notes:
1) Pin READY# has an internal pullup (all C167xx derivatives). This will be documented in the next
revision of the Data Sheet.
2) Timing t28: Parameter description and test changed from 'Address hold after RD#/WR#' to 'Address
hold after WR#'. It is guaranteed by design that read data are internally latched by the controller before
the address changes.
3) During reset, the internal pullups on P6.[4:0] are active, independent whether the respective pins
are used for CS# function after reset or not.
Semiconductor Group
Symbol
Max CPU
= 20
min.
t12
38+tc
instead of
40+tc
t13
63+tc
instead of
65+tc
t38
-7-ta
instead of -
4-ta
t48
38+tc
instead of
40+tc
t49
63+tc
instead of
65+tc
Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh
Clock
Variable
MHz
1/2TCL =
max.
min.
-
2TCL-12+tc
instead of
2TCL -10+tc
-
3TCL-12+tc
instead of
3TCL -10+tc
10-ta
-7-ta
instead of
4-ta
-
2TCL-12+tc
instead of
2TCL -10+tc
-
3TCL-12+tc
instead of
3TCL -10+tc
CPU Clock
Unit
1 to 20 MHz
max.
-
ns
-
ns
10-ta
ns
-
-
ns
-
ns
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