Advertisement
In addition to the description in the C167 Derivatives User's Manual V2.0, the following feature
enhancements have been implemented in the C167CR-LM CB-step and all higher steps:
Incremental position sensor interface
For each of the GPT1 timers T2, T3, T4 of the GPT1 unit, an additional operating mode has been
implemented which allows to interface to incremental position sensors (A, B, Top0). This mode is
selected for a timer Tx via TxM = 110b in register TxCON, x = (2, 3, 4). Optionally, the contents of T5
may be captured into register CAPREL upon an event on T3. This feature is selected via bit CT3 = 1 in
register T5CON.10
Compatibility with previous versions:
In previous versions (e.g. C167CR-LM BA-step), both of the settings (TxM = 110b, T5CON.10 = 1)
were reserved and should not be used. Therefore, systems designed for previous versions will also
work without problems with the C167CR-LM CB-step and all higher steps.
Oscillator Watchdog
The C167CR-LM CB-step and all higher steps provide an Oscillator Watchdog (OWD) which monitors
the clock at XTAL1 in direct drive mode. In case of clock failure, the PLL Unlock/OWD Interrupt
Request Flag (XP3IR) is set and the internal CPU clock is supplied with the PLL basic frequency. This
feature can be disabled by a low level on pin Vpp/OWE. See also C167CR-4RM Data Sheet 7.97.
Bidirectional Reset
The C167CR-LM CB-step and all higher steps allow to indicate an internal watchdog timer or software
reset on the RSTIN# pin which will be driven low for the duration of the internal reset sequence. This
option is selectable by software via bit BDRSTEN/SYSCON.3. After reset, the bidirectional reset option
is disabled (BDRSTEN/SYSCON.3 = 0). See also C167CR-4RM Data Sheet 7.97. Beginning with the
CB-step of the C167CR-LM, RSTIN# will also be driven low for the duration of the internal reset
sequence when this reset was initiated by an external HW reset signal on pin RSTIN#.
Please note also the following functional difference to the C167CR-LM BA-step:
XBUS Peripheral Enable Bit XPEN/SYSCON.2
In the C167CR-LM CB-step and all higher steps, bit SYSCON.2 is a general XBUS Peripheral Enable
bit, i.e. it controls both the XRAM and the CAN module.
Compatibility with previous versions:
When bit SYSCON.2 = 0 (default after reset) in the C167CR-LM CB-step, and an access to an address
in the range EF00h ... EFFFh is made, either an external bus access is performed (if an external bus is
enabled), or the Illegal Bus Trap is entered. In previous versions (e.g. C167CR-LM BA-step), the CAN
module was accessed in this case.
Systems where bit SYSCON.2 was set to '1' before an access to the CAN module in the address range
EF00h ... EFFFh was made will also work without problems with the C167CR-LM CB-step and all
higher steps.
Application Support Group, Munich
Semiconductor Group
Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh
- 11 of 11 -
Advertisement
