Sdram Schematic Diagram - JVC HR-XVC1U Service Manual

A B
8
7
FROM/TO MPEG
MA4
MA3
MA5
MA2
MA6
MA1
MA7 MD15
MA0
MA8
MD14
MA10
MA9
MA11
MCS0#
MRAS#
MPCLK
MD13
MCAS#
MWE#
6
MDQM
MD12
MD8
MD7
MD9
MD6
MD10
MD5
MD11
MD11
MD4
MD12
MD10
MD3
MD13
MD2
MD14
MD1
MD15
MD9
MD0
5
MD8
C4018
0.1 F
MDQM
7
MPCLK
4
MA9
MA8
MA7
MA6
MA5
3
MA4
2
1
A B
C D

SDRAM SCHEMATIC DIAGRAM

S-DRAM
IC4002 HY57V161610DTC-8
0 3.2
VSS VCC
1.0 1.1
MD0
I/O15 I/O0
0.7 1.1
MD1
I/O14 I/O1
1.1 0
VSSQ VSSQ
1.1 1.1
MD2
I/O13 I/O2
0.4 1.0
MD3
I/O12 I/O3
3.2 3.2
VCCQ VCCQ
0 1.1
MD4
I/O11 I/O4
3.2 1.0
MD5
I/O10 I/O5
1.6 0
VSSQ VSSQ
0 0.6
MD6
I/O9 I/O6
0 1.0
MD7
I/O8 I/O7
3.2 3.2
VCCQ VCCQ
1.0
0
MDQM
NC NC DQML
3.3
1.1 3.0
MWE#
DQMU WE
0 3.1
MCAS#
CLK CAS
3.2 3.0
MRAS#
CKE RAS
1.0
2.9
MCS0#
NC NC CS
3.2 1.1
MA11
A9 A11
1.5 1.8
MA10
A8 A10
0.6 1.0
MA0
A7 A0
0 0.5
MA1
A6 A1
0.6 0.6
MA2
A5 A2
0.9 1.0
MA3
A4 A3
0 3.2
VSS VCC
C4019
0.1 F
NOTE: THIS SCHEMATIC DIAGRAM IS THE LATEST AT THE TIME
OF PRINTING AND SUBJECT TO CHANGE WITHOUT NOTICE
C D
2-7
E F
(MPEG PCB)
C4022
0.1 F
C4021
0.1 F
HCB2012K-600T25
NOTE: THE DC VOLTAGE AT EACH PART WAS
MEASURED WITH THE DIGITAL TESTER
DURING PLAYBACK
E F
2-8
G
FROM/TO VIDEO ENCODER
B4002
P.CON+3.3V
DGND
PCB120
VMA236
G
H
8
7
6
5
4
3
2
1
H