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Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
remains virtually constant at a level
GS
known as the plateau voltage, V
times may be approximated by the following:
t
= Q
x R
/(V
− V
r
2
G
GG
GSP
t
= Q
x R
/V
f
2
G
GSP
where
V
= the gate drive voltage, which varies from zero to V
GG
R
= the gate drive resistance
G
and Q
and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
= R
C
In [V
/(V
d(on)
G
iss
GG
t
= R
C
In (V
/V
d(off)
G
iss
GG
POWER MOSFET SWITCHING
) can be made from a
G(AV)
. Therefore, rise and fall
SGP
)
− V
)]
GG
GSP
)
GSP
6000
V
= 0 V
DS
5000
C
iss
4000
3000
C
rss
2000
1000
0
0
5
V
GS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
Figure 7. Capacitance Variation
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NTB30N20
The capacitance (C
a voltage corresponding to the off−state condition when
calculating t
d(on)
on−state when calculating t
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex.
The
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
GG
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
V
= 0 V
GS
T
C
rss
0
15
5
10
V
DS
(VOLTS)
4
) is read from the capacitance curve at
iss
and is read at a voltage corresponding to the
.
d(off)
MOSFET
output
capacitance
= 25°C
J
C
iss
C
oss
20
25
also
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