Bridge-Tied Load (Btl); External Clock - Philips TDA8950 Product Data Sheet

NXP Semiconductors

13.3.2 Bridge-Tied Load (BTL)

13.4 External clock

TDA8950_2
Product data sheet
Maximum output power:
------------------------------------------------------------------ - 2V
R + R
L DSon hs
P = ---------------------------------------------------------------------------------------------------------------------------------------------------------- -
o 0.5%
Maximum output current internally limited to 9.2 A:
2V
P
I = ------------------------------------------------------------------------------------------ -
o peak
R + R
L DSon hs
Where:
•
P : output power at the onset of clipping
o(0.5 %)
•
R : load impedance
L
•
R : high-side R
DSon(hs)
•
R : low-side R
DSon(ls)
•
R : series impedance of the filter coil
sL
•
V : single-sided supply voltage or 0.5
P
•
t : minimum pulse width (typical 150 ns, temperature dependent)
w(min)
•
f : oscillator frequency
osc
Remark: Note that I
o(peak)
of the current through the load and the ripple current. The value of the ripple current is
dependent on the coil inductance and the voltage drop across the coil.
To ensure duty cycle-independent operation, the external clock frequency is divided by
two internally. The external clock frequency is therefore twice the internal clock frequency
(typically 2 350 kHz = 700 kHz).
If several Class D amplifiers are used in a single application, it is recommended that all
the devices run at the same switching frequency. This can be achieved by connecting the
OSC pins together and feeding them from an external oscillator. When using an external
oscillator, it is necessary to force pin OSC to a DC level above SGND. This disables the
internal oscillator and causes the PWM to switch at half the external clock frequency.
The internal oscillator requires an external resistor R
and pin VSSA. R must be removed when using an external oscillator.
OSC
The noise generated by the internal oscillator is supply voltage dependent. An external
low-noise oscillator is recommended for low-noise applications running at high supply
voltages.
R
L
+ R
DSon ls
2R
L
1 t – 0.5 f
w min osc
+ R + 2R
DSon ls
of power stage output DMOS (temperature dependent)
DSon
of power stage output DMOS (temperature dependent)
DSson
should be less than 9.2 A; see
Rev. 02 — 11 June 2009
2 150 W class-D power amplifier
1 t – 0.5 f
P w min osc
sL
(V + V )
DD SS
Section
, connected between pin OSC
OSC
TDA8950
2
(3)
(4)
8.3.2. I is the sum
o(peak)
© NXP B.V. 2009. All rights reserved.
18 of 39