My-99 - Sony HDW-750 Maintenance Manual

HDW-750 (J) : S/N 70001 and Higher
HKDW-703 (UCJ)
CN101 (68/100) 68 SS_BUS_D7
CN101 (67/100) 67 SS_BUS_D6
CN101 (66/100) 66 SS_BUS_D5
CN101 (65/100) 65 SS_BUS_D4
CN101 (64/100) 64 SS_BUS_D3
CN101 (63/100) 63 SS_BUS_D2
CN101 (62/100) 62 SS_BUS_D1
CN101 (61/100) 61 SS_BUS_D0
CN101 (57/100) 57 LOOPREC_RST
CN101 (73/100) 73 DPR_PAD_ST2
CN101 (72/100) 72 DPR_PAD_ST1
CN101 (71/100) 71 DPR_PAD_ST0
CN101 (70/100) 70 SS_L_WR
CN101 (69/100) 69 SS_L_RD
CN101 (60/100) 60
SS_L_PIO_CS2
CN101 (84/100)
84 CK46_LOOP
CN102 (1/7)
1 FPGA_VCC
CN102 (3/7)
3 FPGA_TDO
CN102 (4/7)
4
FPGA_TDI
CN102 (2/7)
2 FPGA_TCK
CN102 (5/7)
5 FPGA_TMS
002 PROM_TDO
002 MASTER_PROGRAM
001,002 MASTER_PROM_DONE
002 MASTER_PROM_INIT
002 MASTER_CCLK
IC143
14
SN74LV125APWR
2 VCC
CN101 (76/100) 76
TDI 1A 1Y
1
1G
5
CN101 (75/100) 75 TCK 2A 2Y
4
002 TCK 2G
9
CN101 (74/100) 74 TMS 3A 3Y
10
002 TMS 3G
12
+3.3V
4A 4Y
13
4G
L_FPGA_WRITE GND
CN102 (6/7)
6 L_FPGA_WRITE 7
Q184
DTA144EE-TL
R183
220k
CN102 (7/7)
7 GND
GND
HDW-750 V2
A B
RB101 RB102
220k 220k
C107
0.1uF
IC103
CXD1095BR
R101
220k
GND
RB103
47
37 61
1 2
D7 H PA7
3 4 36 60
D6 H PA6
35 59
5 6
D5 H PA5
34 58
7 8
D4 H PA4
1 2 33 57
D3 L PA3
30 54
3 4
D2 L PA2
29 53
5 6
D1 L PA1
7 8 28 52
D0 L PA0
RB104
47
38 7
XCLR L PB7
6
R102
1k C104 L PB6
5
470pF
L PB5
4
L PB4
3
GND
L PB3
2
L PB2
1
L PB1
62
L PB0
16
PC7 CL105
15
CL106
PC6
14
PC5 CL107
13
CL108
PC4
12
PC3 CL109
11
PC2 CL110
10
CL111
PC1
9
PC0 CL112
+3.3V-2
RB109 RB110
220k 220k
27
L PD7
26
L PD6
25
L PD5
22
L PD4
21
L PD3
46 20
A2 L PD2
45 19
A1 L PD1
44 18
A0 L PD0
41 51
XWR PE3 CL101
42 50
XRD PE2 CL102
43 48
CL103
XCS PE1
39 47
XDIS PE0 CL104
RB111
220k
GND
C146 C147
0.1uF 0.1uF
+3.3V-2
C144
GND
0.1uF
IC141
CDC509PWR
11 9 R144 47
1G 1Y4
R145 47
8
1Y3
23 5 R146 47
AVCC 1Y2
4 R147 47
1Y1
R148 47
3
1Y0
14 16 R149 47
2G 2Y3
17 R150 47
2Y2
24 20 R151 47
CLK 2Y1
21 R152 47
2Y0
R153 47
13 12
FBIN FBOUT
R142 C145
220k 10pF
NM
GND
+3.3V-2
C141 C142 C143 IC142
R141 R143
0.1uF 0.1uF 0.1uF 4.7k 4.7k XC1802VQ44C
GND 3 21
TDI CEO
7 19
TCK D7
5 14
TMS D6
31 25
TDO D5
10 9
CF D4
15 27
CE D3
13 42
OE/RESET D2
43 29
CLK D1
40
D0
1 24
3 NC1 NC9
2 30
NC2 NC10
4 32
6 NC3 NC11
11 33
NC4 NC12
12 34
8 NC5 NC13
20 37
NC6 NC14
22 39
11 NC7 NC15
23 44
NC8 NC16
C

MY-99 (1/3)

MY-99 (1/3)
+3.3V-2
RB106
220k
PIO_HMC_L_RST
PIO_HMC_L_PWRDWN
PIO_HMC_L_PROGRAM
CL113
PIO_HMC_RTRIG
PIO_HMC_RSTART
CL114
CL115
PIO_HMC_MODE
CL116
PIO_HMC_FRFQ0
PIO_HMC_FRFQ1
PIO_HMC_TIME0
PIO_HMC_TIME1
PIO_HMC_TIME2
CL117
HMC_PIO_WREADY
HMC_PIO_RREADY
HMC_PIO_REND
CL118
MASTER_PROM_DONE
CL119
CL120
CL121
CL122
R184
4.7k
RB112 RB113 RB114 RB108
220k 220k 220k 220k
FPGA_CK46
VDSD_CLK0
VDSD_CLK1
VDSD_CLK2
VDSD_CLK3
VDSD_CLK4
VDSD_CLK5
VDSD_CLK6
VDSD_CLK7
PROM_HMC_D0
4-71 4-71
D E
002
002
002
002
002
002
002
002
002
002
002
002
002
002
001,002
+2.5V
L181
1uH
CN101 (93/100) 93 REG_+2.5V
L182
CN101 (94/100) 94 REG_+2.5V
1uH
CN101 (95/100) 95
REG_+2.5V
CN101 (96/100) 96 REG_+2.5V
C181
22uF
16V
GND
+3.3V
L183
1uH
CN101 (97/100) 97 REG_+3.3V
L184
CN101 (98/100) 98 REG_+3.3V
1uH
CN101 (99/100) 99 REG_+3.3V
CN101 (100/100) 100 REG_+3.3V
C182
22uF
102 101
16V
GND
CN101 (91/100) 91 REG_+2.0V
CN101 (92/100) 92 REG_+2.0V
002
-5V
003 IC144
TC7SH08FU-TE85R
003
003 TP181 R185
220k
DTA144EE-TL
003
5
2
003
CN101 (58/100) 58 LOOPREC_AVTIVE 4
003 1
L_FPGA_WRITE
003
3
003
GND
CL181
CN101 (56/100) 56 L_REC_MODE
CN101 (55/100) 55 LOOPREC_CONECT
GND
CN101 (12/100) 12 GND
CN101 (13/100) 13 GND
CN101 (25/100)
25 GND
CN101 (35/100) 35 GND
CN101 (45/100) 45 GND
CN101 (81/100)
81 GND
CN101 (82/100) 82 GND
CN101 (83/100) 83 GND
CN101 (86/100) 86
GND
CN101 (87/100) 87 GND
CN101 (88/100)
88 GND
CN101 (89/100) 89 GND
CN101 (90/100) 90 GND
GND
002
F G
1
2
3
+3.3V-2 +2.5V-2 +2.5V
C183
GND
0.01uF
NM 8 7 6 5
2 4
+3.3V
1 3
Q181 Q183
R181
SI9953DY-T1
220k
R182
220k
Q182
DTC144EE-TL
-5V
4
5
MY-99 (1/3)
BOARD NO. 1-678-759-12
LOT NO. 083-
HDW-750_MY-99_013_1
H