Sony HDW-750 Maintenance Manual page 160

Diode, Transistor, IC
[DIODE]
GL451VS1
GL451V
[TRANSISTOR]
—TOP VIEW—
DTC114TE (R1=10K)
DTC114TE-TL
R1
—TOP VIEW—
FDC6506P
4 3
5 2
6 1
4 3
S
2
5
S
1
6
—TOP VIEW—
FDC6561AN
4 3
5 2
6 1
4 3
S
2
5
S
1
6
—TOP VIEW—
HN1C03FU-TE85R
(TOSHIBA)
1 6
2 5
3 4
6
1
2
5
3 4
2-6
[IC]
ADS824E/1K (BURR-BROWN)
10-BIT A/D CONVERTER
—TOP VIEW—
INPUTS
BYB : BOTTOM LADDER BYPASS
1 28
BYT : TOP LADDER BYPASS
CLK : CONVERT CLOCK
2 27
IN : ANALOG(+)
IN
: COMPLEMENTARY(_)
3 26
INT
/EXT : REFERENCE SELECT
OE
: OUTPUT ENABLE
4 25
PD : POWER DOWN
REFB : BOTTOM REFERENCE
5 24
REFT : TOP REFERENCE
RSEL : INPUT RANGE SELECT
6 23
VDRV : OUTPUT LOGIC DRIVER SUPPLY VOLTAGE
7 22
OUTPUTS
8 21
BIT1 - BIT10 : DATA BIT
CM : COMMON MODE VOLTAGE
9 20
10 19
11 18
12 17
13 16
14 15
PIN PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO. NO.
1 — 8 O 15
GND BIT7
2 O BIT1(MSB) 9 O BIT8 16
3 O 10 O 17
BIT2 BIT9
4 O 11 O 18
BIT3 BIT10(LSB)
OE
5 O BIT4 12 I 19
6 O 13 I 20
BIT5 PD
7 O BIT6 14 I CLK 21
CLK
14
TIMING
CIRCUITRY
25
10-BIT ERROR
IN
T/H PIPELINED CORRECTION
24
IN A/D CORE
LOGIC
CM
23
INTERNAL
REFERENCE
19 22
REFB REFT
AK6420AM-E2 (ASAHIKASEI ELECT)
2K (128 x 16)-BIT SERIAL EEPROM
—TOP VIEW—
INPUTS
CS
CS
1 8 V
CC
DI
SK BUSY
RESET
2 7 RDY/
SK
DI 3 6 RESET
OUTPUTS
DO
DO 4 5 GND
RDY/
PIN
I/O SIGNAL I/O SIGNAL
NO.
— 22 I
V REFT
CC
— GND 23 O CM
IN
I 24
RSEL I
INT
I 25 I
/EXT IN
I
REFB 26 — GND
I 27 —
BYB V
CC
I
BYT 28 I VDRV
VDRV
28
2 - 11
3-STATE
BIT1 - BIT10
OUTPUTS
18 12
INT OE
/EXT
: CHIP SELECT
: SERIAL DATA
: RESET
: SERIAL CLOCK
: SERIAL DATA
BUSY
: READY/BUSY
HDW-750 V2