Sony HDW-750 Maintenance Manual page 170

IC
HN58V66AFP-10Z (HITACHI)
64K (8192 x 8)-BIT EEPROM
—TOP VIEW—
BUSY
RDY/ 1
28
A12 2 27
A7 3 26
A6 4 25
A5 5 24
A4 6 23
A3 7 22
A2 8 21
A1 9 20
A0 10 19
I/O0 11 18
I/O1 12 17
I/O2 13 16
GND 14 15
LTC1660CGN-E2 (LINEAR TECH)
D/A CONVERTER
—TOP VIEW—
GND 1 16 V
V 2 15 V
OUT A
V 3 14 V
OUT B
V 4 13 V
OUT C
V 5 12 V
OUT D
CLR
REF 6 11
CS
/LD 7 10 D
SCK 8 9 D
2
V
OUT A
DAC A
3
V DAC B
OUT B
4
V DAC C
OUT C
5
V DAC D
OUT D
6
REF
7
CS
/LD
CONTROL
8 LOGIC
SCK
SHIFT REGISTER
9
D
IN
MAX821RUS-T (MAXIM)
VOLTAGE MONITOR
—TOP VIEW—
1 4
GND
RESET
2 3
2-16
INPUTS
A0 - A12 : ADDRESS
V
CC
CE
: CHIP ENABLE
OE
WE : OUTPUT ENABLE
BUSY
RDY/ : READY BUSY
RES
: RESET
RES
WE
: WRITE ENABLE
A8
INPUTS/OUTPUTS
I/O0 - I/O7 : DATA
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
INPUTS
CLR
: ASYNCHRONOUS CLEAR
CC
CS
/LD
: SERIAL INTERFACE CHIP SELECT/LOAD
D
IN : SERIAL INTERFACE DATA
OUT H
REF
: REFERENCE VOLTAGE
SCK
: SERIAL INTERFACE CLOCK
OUT G
OUTPUTS
OUT F
D
OUT : SERIAL INTERFACE DATA
V - V
OUT A OUT H
: DAC ANALOG VOLTAGE
OUT E
OUT
IN
15
V
DAC H OUT H
14
DAC G
V
OUT G
13
DAC F V
OUT F
12
DAC E V
OUT E
11
CLR
ADDRESS
DECODER
10
D
OUT
INPUT
: SET RESET TIMEOUT
SRT
V
CC
OUTPUT
RESET
: ACTIVE-LOW RESET
SRT
ML60851BTB (OKI)
ML60851CTB
USB DEVICE CONTROLLER
—TOP VIEW—
34
35
36
37
38
39
40
41
42
43
44
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
1 I/O D+ 12 O
2 I/O D_ 13 I/O
3 — V 14 I/O
CC
4 I TEST1 15 I/O
5 I TEST2 16 I/O
6 I XIN 17 —
7 O XOUT 18 —
CS
8 I 19 I/O
RD
9 I 20 I/O
WR
10 I 21 I/O
RESET
11 I 22 I/O
INPUTS
A0 - A7 : ADDRESS
ADSEL : ADDRESS INPUT FORMAT SELECT
ALE : ADDRESS LATCH ENABLE
CS
: CHIP SELECT
DACK : DMA ACKNOWLEDGEMENT
RD
: READ
RESET
: RESET
TEST1, TEST2 : TEST
WR
: WRITE
XIN : CRYSTAL OR EXTERNAL CLOCK
OUTPUTS
DREQ
: DMA REQUEST
INTR
: INTERRUPT REQUEST
XOUT : CRYSTAL FEEDBACK
INPUTS/OUTPUTS
AD0 - AD7 : DATA BUS (LSB)/ADDRESS (INPUT)
: DIFFERENTIAL USB DATA
D+, D_
D8 - D15 : DATA BUS (MSB)
6
XIN
DPLL
OSCILLATOR
7
XOUT
PROTOCOL
ENGINE
1
D+
USB
TRANSCEIVER
2
D_
22
21
20
19
18
17
16
15
14
13
12
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
INTR DREQ
23 I ALE 34 O
D15 24 I ADSEL 35 I/O AD7
D14 25 I A7 36 I/O AD6
D13 26 I A6 37 I/O AD5
D12 27 I A5 38 I/O AD4
GND 28 I A4 39 — GND
V 29 I A3 40 — V
CC CC
D11 30 I A2 41 I/O AD3
D10 31 I A1 42 I/O AD2
D9 32 I A0 43 I/O AD1
D8 33 I DACK 44 I/O AD0
STATUS/
CONTROL
22 - 19, 16 - 13
44 - 41, 38 - 35
APPLICATION
INTERFACE
ENDPOINT
FIFO
AND
8-BYTE
SETUP
REGISTER
32 - 25
A0 - A7
D8 - D15
AD0 - AD7
8
CS
9
RD
10
WR
11
RESET
12
INTR
34
DREQ
33
DACK
HDW-750 V2