Sony HDW-750 Maintenance Manual page 171

NM24C16ULEM8X (FSC)
16K-BIT SERIAL EEPROM
—TOP VIEW—
INPUT
SCL : SERIAL CLOCK
NC 1 8 V
CC
INPUT/OUTPUT
NC 2 7 NC
SDA : SERIAL DATA
NC 3 6 SCL
OTHER
NC : NO CONNECTION
GND 4 5 SDA
PCF8574TS-T (PHILIPS)
REMOTE 8-BIT I/O EXPANDER
—TOP VIEW—
INPUTS
INT A0 - A2
1 20 P7
SCL
SCL 2 19 P6
OUTPUT
INT
NC 3 18 NC
INPUTS/OUTPUTS
SDA 4 17 P5
P0 - P7
SDA
V 5 16 P4
CC
OTHER
A0 6 15 GND
NC
A1 7 14 P3
NC 8 13 NC
A2 9 12 P2
P0 10 11 P1
INTERRUPT
1
INT
LOGIC
6
A0
7
A1
9
A2
2
2
SCL
INPUT I C BUS
4
FILTER CONTROL
SDA
POWER-ON
RESET
HDW-750 V2
: ADDRESS
: SERIAL CLOCK LINE
: INTERRUPT OUTPUT
: I/O PORT
: SERIAL DATA LINE
: NO CONNECTION
LP FILTER
10
P0
11
P1
12
P2
14
P3
8
SHIFT I/O
16
REGISTER PORTS
P4
17
P5
19
P6
20
P7
WRITE PULSE
READ PULSE
SI9145BQ-T1 (SILICONIX)
SWITCHMODE CONTROLLER
—TOP VIEW—
V 1 16 V
CC S
MODE SELECT 2 15 OUTPUT
D /SS 3 14 P
MAX GND
COMP 4 13 UVLO
SET
FB 5 12 ENABLE
OTS
NI 6 11
V 7 10 C
REF OSC
GND 8 9 R
OSC
INPUTS
C : SET THE OSCILLATOR FREQUENCY WITH EXTERNAL CAPACITOR
OSC
: CONTROL THE MAXIMUM DUTY CYCLE
D /SS
MAX
ENABLE : ALLOW NORMAL OPERATION (WHEN HIGH), OR STANDBY MODE (WHEN LOW)
FB : INVERTING INPUT OF THE ERROR AMPLIFIER
MODE SELECT : ENABLE MAXIMUM DUTY CYCLE LIMIT AND SET OUTPUT POLARITY CONTROLLER
NI : NON-INVERTING INPUT OF THE ERROR AMPLIFIER
R : EQUIVALENT OF A 1.0-V VOLTAGE SOURCE
OSC
UVLO : MAKE CHIP IN THE STANDBY MODE (WHEN UVLO
SET
OR NORMAL OPERATION (WHEN UVLO
OUTPUTS
COMP : ERROR AMPLIFIER
OTS
: INDICATE AN OVER-TEMPARATURE CONDITION
OUTPUT : DRIVE THE EXTERNAL MOSFET
V : REFERENCE VOLTAGE 1.5 V
REF
OTHERS
P : NEGATIVE RETURN FOR THE V
GND S
V : POSITIVE TERMINAL OF THE POWER SUPPLY
S
1.5 V REFERENCE
1
V
CC
GENERATOR
UVLO
13
UVLO
SET
V
UVLO
12
ENABLE
2
MODE SELECT
3
+
D /SS
MAX
4
_
COMP
ERROR AMP
6
+
NI
+
5
_
FB
_
10
C
OSC
OSCILLATOR
9
R
OSC
VOLTAGE BELOW 1.2 V),
SET
VOLTAGE EXCEED 1.2 V)
SET
SUPPLY
7
V
REF
TEMP
11
OTS
S
SENSE
R
16
V
S
15
DRIVER OUTPUT
LOGIC
14
P
GND
CONTROL
2-17
IC