JVC LT-37M60BU Service Manual page 9

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2.6.2 MAIN CPU PIN FUNCTION [IC7501 : DIGITAL SIGNAL PWB]
Pin Pin name I/O
1 TCK
2 TMS
3 TDI
4 TDO
5 P2.8
6 P2.9
7 P2.10
8 P2.11
9 P2.12
10 P2.13
11 P2.14
12 P2.15
13 VSS33
14 VDD33
15 P4.5
16 A20
17 A19
18 A18
19 A17
20 VSS25
21 VDD25
22 A16
23 A8
24 A7
25 A9
26 A6
27 A5
28 A10
29 A11
30 A12
31 VSS33
32 VDD33
33 A4
34 A3
35 A2
36 A1
37 A0
38 A13
39 ARAS/A14
40 CAS/A15
41 VSS33
42 VDD33
43 MEMCLK
44 CSSDRAM
45 CLKEN
46 CSROM
47 RD
48 UDQM
49 LDQM
50 WR
51 D15 I/O Program ROM data for main CPU
52 VSS33
53 VDD33
54 D7 I/O Program ROM data for main CPU
55 D0 I/O Program ROM data for main CPU
56 D14 I/O Program ROM data for main CPU
57 D8 I/O Program ROM data for main CPU
58 D6 I/O Program ROM data for main CPU
59 D1 I/O Program ROM data for main CPU
60 VSS33
61 VDD33
62 D13 I/O Program ROM data for main CPU
63 D9 I/O Program ROM data for main CPU
64 D5 I/O Program ROM data for main CPU
Function
I Test purpose
I Test purpose
I Test purpose
O Test purpose
O Not used
O Blue for OSD
O Blue for OSD
O Blue for OSD
O Blue for OSD
O Blue for OSD
I Not used
O Request for chassis CPU communication
- GND
I 3.3V
O Not used
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
- GND
I 2.5V
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
- GND
I 3.3V
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
O Program ROM address for main CPU
- GND
I 3.3V
O Clock for memory
O Chip select for memory
O Clock enable for memory
O Chip select for memory
O Read for memory
O Control buffer of memory
O Control buffer of memory
O Write for memory
- GND
I 3.3V
- GND
I 3.3V
Digitized in Heiloo Netherland
Pin Pin name I/O
65 D2 I/O Program ROM data for main CPU
66 D12 I/O Program ROM data for main CPU
67 D10 I/O Program ROM data for main CPU
68 VSS33 - GND
69 VDD33 I 3.3V
70 D4 I/O Program ROM data for main CPU
71 D3 I/O Program ROM data for main CPU
72 D11 I/O Program ROM data for main CPU
73 RSTIN I Reset
74 POWER O Sleep state release for chassis CPU [Relese : L]
75 P3.1 O Not used
76 REMOCON I Remote control
77 P3.3 I Clock for OSD
78 P3.4 O Red for OSD
79 P3.5 O Red for OSD
80 P3.6 O Red for OSD
81 P3.7 O Red for OSD
82 MTST O Data transmission for chassis CPU communication
83 MTSR I Data receive for chassis CPU communication
84 VSS33 - GND
85 VDD33 I 3.3V
86 VSS25 - GND
87 VDD25 I 2.5V
88 TXD0 O Communication for adjustment
89 RXD0 O Communication for adjustment
90 P3.12 O Red for OSD
91 CLK O Clock for chassis CPU communication
92 P3.15 O Green for OSD
93 P5.14 O Green for OSD
94 P5.15 O Green for OSD
95 TRIG_IN O Green for OSD
96 TRIG_OUT O Green for OSD
97 P6.2 O Green for OSD
2
98 P6.3 O I C bus clock (for main memory)
2
99 P6.4 I/O I C bus Data (for main memory)
100 P6.5 O Teletext signal select [Analog RGB : H / Digital RGB : L]
101 IRQ O Not used
102 VSYNC I Vertical sync
103 HSYNC I Horizontal sync
104 COR/RSTOUT O Not used
105 BLANK O Ys for OSD / Teletext
106 VDD33 I 3.3V
107 VSS33 - GND
108 XTAL1 I 6MHz for system clock
109 XTAL2 O 6MHz for system clock
110 VSSA - GND
111 VDDA I 2.5V
112 R O R for OSD / Teletext
113 G O G for OSD / Teletext
114 B O B for OSD / Teletext
115 VSSA - GND
116 VDDA I 2.5V
117 CVBS2 I Video for Teletext
118 VSSA - GND
119 VDDA I 2.5V
120 CVBS1B I Video for Teletext
121 CVBS1A I Video for Teletext
122 VSSA - GND
123 VDDA I 2.5V
124 KEY1 I Key scan data 1 [ON : H]
125 KEY2 I Key scan data 2 [ON : H]
126 MECA_SW I Main power ON / OFF control [ON : L]
127 P5.3 I Not used
128 TMODE I Test purpose
4/19/2017
Function
(No.YA360)1-9