Integra DTR-7.8 Service Manual page 188

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -86
Q1002: IS25C02(2 kbit EEPROM)
BLOCK DIAGRAM
SI
CS
WP
SCK
PIN CONFIGURATION
TERMINAL DESCRIPTION
STATUS
REGISTER
DATA
REGISTER
MODE
DECODE
LOGIC
CLOCK
HOLD
CS 1 8
SO 2 7
WP 3 6
GND 4 5
CS Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
V Power
CC
WP Write Protect
HOLD Suspends Serial Input
GND
VCC
256 x 8/512 x 8
MEMORY ARRAY
ADDRESS
DECODER
VCC
HOLD
SCK
SI
DTR-7.8
OUTPUT
BUFFER
SO