Integra DTR-7.8 Service Manual page 109

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -7
Q3041 : CS42516-CQZ (192 kHz, 6-Ch Codec with S/PDIF Receiver)
BLOCK DIAGRAM
RXP0
RXP1/GPO1
RXP2/GPO2
RXP3/GPO3
RXP4/GPO4
RXP5/GPO5
RXP6/GPO6
RXP7/GPO7
MUTEC
FILT+
VQ
Ref
REFGND
VA
AGND
AINL+
AINL-
AINR+
AINR-
AOUTA1+
AOUTA1-
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
AOUTB2-
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-
PIN CONFIGURATION
TXP VARX AGND LPFLT
Clock/Data
Rx
Recovery
GPO
MUTE
ADC#1
Digital Filter
ADC#2
Digital Filter
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
1
CX_SDIN1
CX_SCLK 2
CX_LRCK 3
VD 4
DGND 5
6
VLC
7
SCL/CCLK
CS42516
8
SDA/CDOUT
9
AD1/CDIN
10
AD0/CS
11
INT
12
RST
13
AINR-
14
AINR+
15
AINL+
16
AINL-
DGND DGND VD VD
C&U Bit
Data Buffer
S/PDIF
Decoder
Format
Detector
Internal MCLK
DEM
Gain & Clip ADC
Serial
Data
Gain & Clip
48
RXP1/GPO1
47
RXP2/GPO2
46
RXP3/GPO3
45
RXP4/GPO4
44
RXP5/GPO5
43
RXP6/GPO6
42
RXP7/GPO7
41
VARX
40
AGND
39
LPFLT
38
MUTEC
37
AOUTA1-
36
AOUTA1+
35
AOUTB1+
34
AOUTB1-
33
AOUTA2-
INT
RST
Control
AD0/CS
Port
AD1/CDIN
SDA/CDOUT
SCL/CCLK
VLC
OMCK
Mult/Div RMCK
Serial
SAI_LRCK
Audio
SAI_SCLK
Interface
SAI_SDOUT
Port
VLS
ADCIN1
ADCIN2
CX_SDOUT
CX_LRCK
CX_SCLK
CX_SDIN1
CX_SDIN2
CX_SDIN3
DTR-7.8