Yamaha R-1330 Service Manual page 54

A B C
R-1330/NS-BP400
MAIN 1/4
1
Page 51 I7
to FRONT (4)_CB805
2
MAIN (1)
3
to MAIN 3/4
to MAIN 4/4
to MAIN 3/4
4
to MAIN 2/4
5
CB53
6
Page 51 E8
to FRONT (1)_CB801
7
10.6 12.0
10.6
8
0
IC56
0 0
0.7
0.7
0
0
IC56
0
9
-11.4
-11.8
IC52: M24C08-RDW6TP
8 K-bit and 1 K-bit serial I 2 C bus EEPROM
V CC
10
3
E0-E2 SDA
M24Cxx
SCL
V SS
WC
V SS
54
D E F
IPOD IN
TO:CD PLAYER
2.7 0
SYSTEM
0
2.7
CONNECTOR
0 5.0 0 0
5.0 0
0 5.0
0
5.0
0
0
0
MICROPROCESSOR
0.3
IC50
4.5
2.4
1.1
1.9
0
5.0
B
5.0
5.0
2.4
0 0
5.0
4.1
3.5
5.0
0
0
5.0
5.0
0
0
0
5.0
0
0
0
0
5.0
0
0
IC55: NJM4580V-TE2
to MAIN 4/4
Dual operational amplifier
IC53: RH5RE58AA-T1-FA
IC54: TC74VHCT08AFT
V+
Voltage regulator
Quad 2-input AND gate
V V
IN OUT
2 3 1A 1 14 Vcc
2, 6
1B 2 13 4B –INPUT
NC 1 8 V CC
+INPUT
1Y 3 12 4A
NC 2 7 WC
3, 5
+
E2 3 6 SCL
2A 4 11 4Y
4 5 SDA –
2B 5 10 3B
Vref
2Y 6 9 3A
1 GND 7 8 3Y V–
GND
G H
Page 53 L2
to FRONT (3)_CB302
to MAIN 2/4 to MAIN 3/4
5.0
3.8
5.0
5.0 0
5.0
3.5
3.8
3.8
0
5.0
5.0
0
5.0
0
0
0
0
0
0
0
0
0
0
0
0
0
5.0 0
5.0 0
0
5.0
3.5
IC58
0
0
EEPROM
5.0
0
IC59
0
POINT B XL50 (Pin 13 of IC50)
0
5.0
0 IC60
0
0
0
IC56: BA15218F
Dual high slew rate, low noise operational amplifier
8
OUT1 1 8 V CC
1, 7 – IN1 2 7 OUT2
OUTPUT 1ch
– +
2ch
+ IN1 3 + – 6 – IN2
V 4 5 + IN2
EE
4
I J K
Page 52 C6
to FRONT (2)_W1
1 2
C
5.0 IC53
5.0
0 5.8 7.8
0
0
0
to MAIN 2/4
to MAIN 4/4
12.0
5.0
5.6
5.0 5.0
5.0
4.3
5.0
5.0
5.0
-11.5
5.0
5.0
IC50: M3062LFGPFP
4.9 4.9 Single-chip 16-bit microprpcessor
4.9
5.0
8 8 8
-11.5
Port P0 Port P1 Port P2 Port P3
<VCC2 ports>
Internal peripheral functions
(10-bit X 18-channels
Timer (16-bit) Expandable up to 26 channels)
Output (timer A): 5
Input (timer B): 6 clock synchronous serial I/O
(8 bits x 3-channels)
Three-phase motor
control circuit CRC arithmetic circuit (CCITT)
IC59, 60: TC7SET32FU
IC58: TC7SH08FU (Polynomial : X
2-input OR gate
2-input AND gate
M16C/60 series 16-bit
Microprocessor core
Watchdog timer R0H
R1H
IN B 1 5 (15-bit)
V
IN B 1 5 V CC
CC
DMAC
(2-channels)
IN A
2
IN A 2
D/A converter
(8 bits x 2 channels)
OUT Y
GND 3 4
GND 3 4 OUT Y
★ All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★ Components having special characteristics are marked
with parts having specifications equal to those originally installed.
★ Schematic diagram is subject to change without notice.
L M N
5.0
IC55
2.5
2.5
IC55
2.5
0
2.5
IC55
2.5 2.5
0
0
0
0
IPOD IN
CB702
MAIN (2)
POINT C 1 /+5M, 2 / N-RST of CB51
+5M 1 +5M 1
N-RST N-RST 2
2
POWER cable ON POWER cable OFF POWER cable ON
8 8 8 8
Port P4 Port P5 Port P6
<VCC1 ports>
A/D converter System clock
generation circuit
XIN-XOUT
UART or XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Clock synchronous serial I/O
16 +X 12 +X +1) 5 (8 bits x 2 channels)
Memory
ROM
R0L SB
256K
R1L USP
R2 RAM
R3 ISP 20K
INTB
A0 PC
A1
A1
FB
FB FLG
Multiplier
● 電圧は、内部抵抗 10MΩの電圧計で測定したものです。
and must be replaced ● 印のある部品は、安全性確保部品を示しています。部品の交換が必要な場合、
パーツリストに記載されている部品を使用してください。
● 本回路図は標準回路図です。改良のため予告なく変更することがございます。