Table of Contents
Advertisement
Alto Hardware Manual
. Section 8: Control
RAM,
ROM,
and
s
Registers
61
Note that the function code is different for emulator and non-emulator tasks:
ESRB~
is F1=15 and is
defined only in the emulator task, while SRB .. is F1= 13 and is defined in all RAM-related tasks besides
the emulator .. (Fl=13 corresponds to
RMR~
in the emulator.
In Altos without the 3K RAM option,
F1=13 performs
RMR~
in all RAM-related tasks, including the emulator.)
The register bank numbers are all reset to zero by a reset (bootstrap) operation, thereby causing the Alto
to behave the same as a standard Alto with a single bank of S registers shared among all RAM-related
tasks.
8.8
Restrictions and Caveats
1.
Both RDRAM and WRTRAM cause the microprocessor's system clock to stop for one cycle. This may
yield unspecified results if the system clock is also stopped for some other reason (e.g., waiting for
memory data).
As a general rule, the system clock should run without hesitation during the
microinstruction following a RDRAM or WRTRAM, except for the effect of the RDRAM or WRTRAM itself.
On Alto I, there is an additional timing problem which manifests itself in some machines, for example, in
the following microcode sequence:
MAR"FOO;
Starts memory reference
T" FIE;
Loads the control RAM address register
L .. MD, WRTRAM;
Save away the high-order word in M
L" MD;
Completes the write into the RAM
What happens is that the last instruction suspends the system clock for one microinstruction, and some
Alto I memories cannot keep the memory data good for two microinstruction times, so a parity error may
occur. The data is actually stored in the RAM at the end of the first microinstruction time, so there is
probably no error in the data even if a parity interrupt subsequently occurs. This "phantom" parity error
may be averted by the following code, which takes three more microinstruction times, but does not
invoke the horrendous microcode overhead of parity error recording:
MAR" FOO;
NOP;
L~MD;
T~MD;
TEMP" L, L"T;
T"FIE, WRTRAM;
L<-TEMP;
Starts memory reference
Required for· memory timing
Save away the low-order word
Save away the high-order word
. Loads the address register, starts the write.
Complete the write into the RAM
2. Unlike the control RAM, which can be addressed from 2 places, the control ROM gets its address only
from the MPC RAM.
Consequently, to read ROM location x, the instruction following the one with
F1
=
12B (RDRAM) must reside at location (x mod 1024).
Therefore, you'll probably want to put the
"reading" code in the RAM:
T<-ACl, RDRAM,
:X;
X:
L" ALLONES;
ACO~L,
...
Only ACl[4-5] are relevant
Here the read takes place
Note also that only RaMO can be read by these means.
There is no known way to read RaMI.
3. Some Alto Is have been observed not to evaluate the BUS=O function correctly when reading an S-
register during the first microinstruction after a task switch. The same operation in other than the first
microinstruction causes no difficulty.
Advertisement
Table of Contents
