Aaeon EMB-CV2 Manual page 66

M i n i - I T X
CR F7h. (WDTO# Control & Status Register; Default 00h)
BIT READ/WRITE
7 R/W
6 R/W
Write "1" Only
5
R/W
4
Write"0"Clear
3~0 R/W
01h: Time-out occurs after 1 second/minute
02h: Time-out occurs after 2 second/minutes
03h: Time-out occurs after 3 second/minutes
...........................................................
FFh: Time-out occurs after 255 second/minutes
Mouse interrupt reset watch-dog timer enable
0: Watchdog timer is not affected by mouse interrupt.
1: Watchdog timer is reset by mouse interrupt.
Keyboard interrupt reset watch-dog timer enable
0: Watchdog timer is not affected by keyboard interrupt.
1: Watchdog timer is reset by keyboardd interrupt.
Trigger WDTO# event. This bit is self-clearing.
WDTO# status bit
0: Watchdog timer is running.
1: Watchdog timer issue time-out event.
These bits select IRQ resource for WDTO#. (02h for
SMI# event.)
Appendix A Programming the Watchdog Timer
E M B - C V 2
DESCRIPTION
A-5