Theory Of Operation; Block Diagram Description; Detailed Circuit Description; Main Trigger Generator - Tektronix 7B92A Maintenance Manual

500 mhz dual timebase plug-in
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This section of the manual contains a description of the
circuitry used in the 7B92A. The description begins with
a discussion of the instrument using the block diagram in
the Diagrams section. Each circuit is then described in
detail with a block diagram provided to show the major
interconnections between circuits, and the relationship of
the front-panel controls to each circuit.

BLOCK DIAGRAM DESCRIPTION

The Main Trigger Generator ensures a stable crt
display by starting each sweep at the same point on the
waveform. The output of the Main Trigger Generator is a
fast-rise pulse which starts the Delaying Sweep
Generator.
The Delaying Sweep Generator produces a
linear voltage ramp. This ramp is displayed when the
time base is in the Intensified or Alternate mode. The
Delaying Sweep ramp is also used as a delay-time
reference when the time base is in the Alternate or
Delayed mode. The delay time is set by the slope of the
Delaying Sweep ramp and the Delay Pick off comparator
voltage. When the time base is in the Normal Sweep
mode, the comparator voltage is set to 0 (zero) and the
Delay Pick off outputs a pulse when the Delaying Sweep
ramp starts.
The Delayed Trigger Generator produces a fast-
rise pulse to start the Delayed Sweep Generator. When
the Delayed Trigger Generator is in the Runs After Delay
Time mode, the pulse from the Delay Pick off produces
the Delayed Trigger output pulse. When the Delayed
Trigger Generator is in the Triggerable After Delay Time
mode, the pulse from the Delay Pick off enables the
Delayed Trigger Generator, which then processes the
input signal in the same way as the Main Trigger
Generator.
The Delayed Sweep Generator produces a linear
voltage ramp that is displayed as either the Normal or
Delayed sweep.
The Horizontal Logic controls the Main Trigger
Generator, the Delayed Trigger Generator, and the
Output Amplifier.
The Horizontal Logic produces a
Trigger Disable pulse which resets the trigger generators
and allows the sweep generators to reset and stabilize
before starting another ramp. The Horizontal Logic also
controls which sweep ramp is passed through the Output
Amplifier to be displayed.

THEORY OF OPERATION

crt display and couples the proper sweep ramp(s) to the
oscilloscope.

Main Trigger Generator

The Main Trigger Generator provides a stable display by
starting the Delaying Sweep Generator at a selected
point on the input waveform. The triggering point can be
varied by the LEVEL control and may be on either the
positive or negative slope of the waveform. The input
signal may be the waveform being displayed (INT), a
waveform from an external source (EXT or EXT'10), or a
sample of the power-line voltage (LINE).
set by the COUPLING switches. Dc coupling provides a
bandwidth of dc to 500 megahertz. Ac coupling blocks
dc and frequencies below about 30 hertz. AC LF REJ
(ac
frequencies above 30 kilohertz.
coupling, high-frequency rejection) passes frequencies
between 30 hertz and 30 kilohertz.
external trigger signal is connected to the Main Trigger
Generator through the MAIN TRIG IN connector, J100.
The input impedance at J100 can be set to either 1
megohm or 50 ohms by TERM switch S205.
energizes and applies the trigger signal to C11 and R11.
Signals below 30 kilohertz are connected to the gate of
Q22A through R14, C12, R12, and R11.
between 30 kilohertz and 100 megahertz are connected
to the gate of Q22A through R17 and C11.
signals pass through Q22A and Q24 to pin 3 of U74.
Signals above 100 megahertz are connected to pin 4 of
U74 through C20. (Pins 3 and 4 of U74 are internally
connected.)
K6 de-energizes and applies the input signal to C10 and
R9.
applied to the gate of Q22A.
3-1
The Output Amplifier horizontally positions the

DETAILED CIRCUIT DESCRIPTION

The bandwidth of the Main Trigger Generator is
coupling,
low-frequency
External Source (SN B070000-above).
If the SOURCE switch is set to EXT, relay K6
If the SOURCE switch is set to EXT . 10, relay
The signal is then divided by 10 before being
Section 3-7B92A
rejection)
passes
AC HF REJ (ac
The
Signals
These

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