Ssm Interface; External Pll Pins; Global Pins; Jtag Interface - Yamaha RX-V475 Service Manual

SSM Interface

Pin No. Function Name
D12
C12
B12
A12
SSMD[7:0]
D11
C11
B11
A11
C10 SSMCLK
A13 SSMCMD
D10 SSMCP
D9 SSMWP

External PLL Pins

Pin No. Function Name
J2
VCO[1:0]
K2
J1
PDOUT[1:0]
K1

Global Pins

Pin No. Function Name
D13 NRESET
K3 XTALI
J3 XTALO
C7 RREF
B10 TEST1
A10 HIGHZ
E4
F4
G4
H4
J4
V1
n.c.
A4
A5
B4
B5
C8
C9

JTAG Interface

Pin No. Function Name
B15 TMS
C14 TCK
A16 TDI
A15 TDO
I/O
I/O Data lines.
O Clock output.
O Command output.
I Card power input (high = off).
I Write protect input (low = protect).
I/O
External oscillator inputs, typically coming from an external VCO. Together with the external loop-filter and
I
the internal clock dividers, each PDOUT/VCO pair can form a complete PLL.
Phase discriminator outputs. These signals are charge-pump type outputs.
O
Each of them can be used to feed the loop-filter of a PLL structure.
I/O
Reset (active low). When asserted, the chip is placed in the reset state and the peripheral pins are
configured as inputs. After deassertion of NRESET, the chip is clocked by XTALI and starts booting from the
I
port configured by the FCLE, FALE pins.
The NRESET signal must be asserted after power-up.
I Oscillator circuit input. Internal system clock will be derived from XTALI (internal clock multiplier).
O Oscillator circuit output.
I Reference current. Connect a 3.0 k-ohms ±1% resistor to GND.
I Reserved. Connect to VDD for normal operation.
I Reserved. Connect to VDD for normal operation.
– Pins must be left unconnected (18x).
I/O
I JTAG mode select.
I JTAG clock.
I JTAG serial data input.
O JTAG serial data output.
RX-V475/HTR-4066/RX-V500D
Detail of Function
Detail of Function
Detail of Function
Detail of Function
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