Nand-Flash Interface; Ethernet Mac-Phy Interface (Mii) - Yamaha RX-V475 Service Manual

Pin No. Function Name
H18
J17
J16 NCS[3:0]
J15
K17 NOE
K16 NWE
K18 NWAIT
K15 MEMCLK
J18 MEMCKE

NAND-Flash Interface

Pin No. Function Name
T17
T16
T15
R17
FD[7:0]
R16
R15
P16
P15
V18 FALE
U16 FCLE
U15 NFCE0
U18 NFRB
V17 NFRE
U17 NFWE
V16 NFWP

Ethernet MAC-Phy Interface (MII)

Pin No. Function Name
U14 MIIDIO
V14 MIIMDC
V13 MIIRXD[3]
U13 MIIRXD[2]
V12 MIIRXD[1]
U12 MIIRXD[0]
T12 MIIRXCLK
R13 MIIRXER
T14 MIIRXDV
V11 MIITXD[3]
U11 MIITXD[2]
V10 MIITXD[1]
U10 MIITXD[0]
R12 MIITXCLK
T11 MIITXER
R11 MIITXEN
T13 MIICOL
R14 MIICRS
V15 MIIPHYCLK
I/O
Chip select signals. The active memory range for NCS[n] (active low) can be configured.
• NCS[0] supports SRAM, can be used for booting.
O • NCS[1] supports SDRAM or SRAM.
• NCS[2] supports SRAM.
• NCS[3] supports SRAM.
O Output enable, asserted (low) for read operations.
O Write enable, asserted (low) for write operations.
I
External wait line. If NWAIT is asserted, memory access will be stalled. Can be configured as either low-
active (default) or high-active.
O SDRAM system clock.
O SDRAM clock enable.
I/O
I/O Bi-directional data bus.
O Address latch enable; pull-up/down defines boot mode.
O Command latch enable; pull-up/down defines boot mode.
O Chip-enable, low-active.
I Ready/busy. NAND flash is busy when NFRB is low.
O Read enable, low-active.
O Write enable, low-active.
O Write protect, low-active.
I/O MII
I/O Management data
O Management clock
I RxD 3
I RxD 2
I RxD 1
I RxD 0
I Receive clock
I Receive error
I Receive data valid
O TxD 3
O TxD 2
O TxD 1
O TxD 0
I Transmit clock
O Transmit error
O Transmit data enable
I MII ethernet collision
I MII carrier sense
O 25.000 MHz clock
RX-V475/HTR-4066/RX-V500D
Detail of Function
Detail of Function
RMII
Management data
Management clock
RxD 1
RxD 0
Receive error
Carrier sense/data valid
TxD 1
TxD 0
Transmit data enable
50.000 MHz clock
SMII
Rx-Sync
RxD
Receive clock
Tx-Sync
TxD
Transmit clock
125.000 MHz clock
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