Aiwa XR-DV3M Service Manual page 77

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Pin No. Pin Name
41 TRDR
42 FFDR
43 FRDR
44 VDD
45 VSS
46 TEST
47 TES1
48 XTSL
49 VC
50 FE
51 SE
52 TE
53 CE
54 RFDC
55 ADIO
56 AVSS0
57 ICEN
58 AVDD0
TE
L 13942296513
59 ASYO
60 ASYI
61 RFAC
62 AVSS3
63 CLTV
64 FILO
65 FILI
66 PCO
67 AVDD3
68 BIAS
69 VCTL
70 V16M
71 VPCO
72 VSS
73 MD2
74 DOUT
75 ASYE
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76 VDD
77 LRCK
78 LRCKI
.
79 PCMD
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I/O
O Tracking drive output.
O Focus drive output.
O Focus drive output.
— Digital power.
— Digital ground.
I Test terminal. Normally ground.
I Test terminal. Normally ground.
Crystal selection input terminal. Sets "L" when crystal is 16.9344 MHz. Sets "H" when crystal
I
is 33.8688 MHz.
I Center voltage input.
I Focus error signal input.
I Sled error signal input.
I Tracking error signal input.
I Center servo analog input.
I RF signal input.
O Not used.
— Analog ground.
I Constant current input for OP amplifier.
— Analog power.
O EFM full-swing output. ("L" = VSS, "H" = VDD)
I Asymmetry comparator voltage input.
I EFM signal input.
— Analog ground.
I VCO1 control voltage input for doubling.
O Filter output for master PLL (slave = digital PLL).
I Filter input for master PLL.
O Charge pump output for master PLL.
— Analog power supply.
I Asymmetry circuit constant current input.
I VCO2 control voltage input for wide band EFM PLL.
VCO2 oscillator output for band range EFM PLL. Clock input for wide band EFM PLL
I/O
switched by command.
O Charge pump output for wide band EFM PLL.
— Digital ground.
I Digital-out ON/OFF control ("L" = OFF, "H" = ON).
O Digital-out output terminal.
I Asymmetry circuit ON/OFF ("L" = OFF, "H" = ON).
— Digital power.
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O D/A interface. LR clock output f = Fs.
y
I D/A interface. LR clock input.
i
O D/A interface. Serial data output (2's COMP, MSB fast).
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