Aiwa XR-DV3M Service Manual page 60

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Pin No. Pin Name
168 XTL1
169 XRST
170 VDDS
171 D0
172 D1
173 D2
174 D3
175 D4
176 D5
177 D6
178 D7
179 VSS
180 A0
181 A1
182 A2
183 A3
184 A4
185 VDD
186 A5
TE
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187 A6
188 A7
189 A8
190 VSS
191 A9
192 A10
193 A11
194 A12
195 A13
196 A14
197 VDD5V
198 XWAIT
199 XRD
200 XWR
201 XCS
202 VSS
203 VDD
204 XINIT0
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205 XINIT1
206 MDB0
207 MDB1
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208 MDB2
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I/O
I Terminal to connect external crystal oscillator between XTL1 and XTL2.
I Chip reset negative logic input signal.
— Standard 5.0 V digital power supply terminal.
I/O 8 bit data bus [0].
I/O 8 bit data bus [1].
I/O 8 bit data bus [2].
I/O 8 bit data bus [3].
I/O 8 bit data bus [4].
I/O 8 bit data bus [5].
I/O 8 bit data bus [6].
I/O 8 bit data bus [7].
— Digital ground terminal.
I Input signal [0] of address selection sub-CPU CXD1866 internal register.
I Input signal [1] of address selection sub-CPU CXD1866 internal register.
I Input signal [2] of address selection sub-CPU CXD1866 internal register.
I Input signal [3] of address selection sub-CPU CXD1866 internal register.
I Input signal [4] of address selection sub-CPU CXD1866 internal register.
— Standard 3.3 V digital power supply terminal.
I Input signal [5] of address selection sub-CPU CXD1866 internal register.
I Input signal [6] of address selection sub-CPU CXD1866 internal register.
I Input signal [7] of address selection sub-CPU CXD1866 internal register.
I Input signal [8] of address selection sub-CPU CXD1866 internal register.
— Digital ground terminal.
I Input signal [9] of address selection sub-CPU CXD1866 internal register.
I Input signal [10] of address selection sub-CPU CXD1866 internal register.
I Input signal [11] of address selection sub-CPU CXD1866 internal register.
I Input signal [12] of address selection sub-CPU CXD1866 internal register.
I Input signal [13] of address selection sub-CPU CXD1866 internal register.
I Input signal [14] of address selection sub-CPU CXD1866 internal register.
— Terminal for power supply of 5 V withstand voltage. Supplies standard 5.0 V.
O Not used.
I Strobe negative logic input for register writing.
I Strobe negative logic input for register state reading.
I Strobe negative logic input for register status reading the chip inside the sub-CPU.
— Digital ground terminal.
— Standard 3.3 V digital power supply terminal.
O Interrupt request negative logic output to sub-CPU from read channel block.
O Interrupt request negative logic output to sub-CPU from decoder block and authentication block.
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I/O DRAM data bus [0].
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I/O DRAM data bus [1].
i
I/O DRAM data bus [2].
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