Aiwa XR-DV3M Service Manual page 74

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IC, MC44724A
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Pin No. Pin Name
1 CVBS/Cb/B1
______________________
2 CVBS/Cb/B1
3 CVBS/Cb/B1Vdd
4 Y/G1
_________
5 Y/G1
6 Y/G1Vdd
7 C/Cr/R1
______________
8 C/Cr/R1
9 C/Cr/R1Vdd
10 DAVss
11 Ibias1
12 Vref1
13 DAVdd
14 Vref2
15 Ibias2
16 NC
17 CVBS/Cb/B2
_______________________
18 CVBS/Cb/B2
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L 13942296513
19 CVBS/Cb/B2Vdd
20 Y/G2
_________
21 Y/G2
22 Y/G2Vdd
23 C/Cr/R2
______________
24 C/Cr/R2
25 C/Cr/R2Vdd
26 ChipA
27 TEST
28 DVss
29 CLOCK
30 DVdd
31 Reset
___________
32 PAL/NTSC
33 SO
34 SDA/SI
35 SCL/SCK
36 SEL
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37 DVdd
38 DVss
.
39-46 DVIA7-0
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I/O
O Analog composite video signal output or Cb or B signal output current drive (positive).
O Analog composite video signal output or Cb or B signal output current drive (negative).
I Power Supply for CVBS/Cb/B DAC1 circuit.
O Analog luminance or G signal output drive (positive).
O Analog luminance or G signal output drive (negative).
I Power Supply for Y/G DAC1 circuit.
O Analog chrominance signal output or Cr or R signal output current drive (positive).
O Analog chrominance signal output or Cr or R signal output current drive (negative).
I Power Supply for C/Cr/R DAC1 circuit.
I Ground for DAC circuit.
O Reference current for the 1st set of 3 DACs.
I Reference full scale voltage for the 1st set of 3 DACs.
I Power Supply for the DACs.
I Reference full scale voltage for the 2nd set of 3 DACs.
O Reference current for the 2nd set of 3 DACs.
— No Connect to pin.
O Analog composite video signal output or Cb or B signal output current drive (positive).
O Analog composite video signal output or Cb or B signal output current drive (negative).
I Power Supply for CVBS/Cb/B DAC2 circuit.
O Analog luminance or G signal output current drive (positive).
O Analog luminance or G signal output current drive (negative).
I Power suuply for Y/G DAC2 circuit.
O Analog chrominance signal output or Cr or R signal output current drive (positive).
O Analog chrominance signal output or Cr or R signal output current drive (negative).
I Power Supply for C/Cr/R DAC2 circuit.
2
I I C chip address select {0 : 40 (hex) /41 (hex) 1 : 1D (hex) /1E (hex)}.
I TEST pin (Grounded).
I Ground for Digital circuit.
I 27MHz clock input.
I Power Supply for Digital circuit.
I Reset signal, active LOW.
I NTSC/PAL select. This pin is sampled only at Reset. (NTSC : Low PAL : High).
O IN SPI mode, serial data output/In I2C mode, Grounded.
I/O Serial data input, Open drain output/ If SPI mode, serial data input.
I Serial clock.
I Connect to Ground/If SPI mode, this pin is chip select.
I Power Supply for Digital circuit.
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I Ground for Digital circuit.
y
8-bit Multiplexed 4:2:2 data (ITU Rec656/601) input (DVIA), or Multiplexed Y data (ITU
i
I/O
Rec656/601) input in 16-bit input mode.
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