Aiwa XR-DV3M Service Manual page 57

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Pin No. Pin Name
42 VDDS
43 HDB6
44 HDB9
45 HDB5
46 VSS
47 HDBA
48 HDB4
49 HDBB
50 HDB3
51 VDDS
52 VDD
53 HDBC
54 HDB2
55 VSS
56 HDBD
57 HDB1
58 HDBE
59 HDB0
60 HDBF
TE
L 13942296513
61 HDRQ
62 VDDS
63 VSS
64 XHWR
65 XHRD
66 REDY
67 VDD
68 XHAC
69 HINT
70 XS16
71 VSS
72 HA1
73 XPDI
74 VDDS
75 HA0
76 HA2
77 HCS0
78 HCS1
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79 DASP
80 VSS
81 C2PO
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82 XRCI
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I/O
— Standard 5.0 V digital power supply terminal.
I/O Host data bus [6].
I/O Not used.
I/O Host data bus [5].
— Digital ground terminal.
I/O Not used.
I/O Host data bus [4].
I/O Not used.
I/O Host data bus [3].
— Standard 5.0 V digital power supply terminal.
— Standard 3.3 V digital power supply terminal.
I/O Not used.
I/O Host data bus [2].
— Digital ground terminal.
I/O Not used.
I/O Host data bus [1].
I/O Not used.
I/O Host data bus [0].
I/O Not used.
O Positive logic output circuit of DMA data request to host.
— Digital power supply terminal of standard 5.0 V.
— Digital ground terminal.
I Negative logic input signal of data write strobe from host.
I Negative logic input signal of data read strobe from host.
O Not used.
— Standard 3.3 V digital power supply terminal.
I DMA acknowledge negative logic input signal from host.
I/O
Not used.
O
— Digital ground terminal.
I Address input signal for internal register selection [1].
I/O Open drain signal. Connected to PDIAG terminal of ATAPI.
— Digital power supply terminal of standard 5.0 V.
I Address input signal for internal register selection [0].
I Address input signal for internal register selection [2].
I Chip selection negative logic input signal from host [0].
I Chip selection negative logic input signal from host [1].
I/O Not used.
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— Digital ground terminal.
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I C2 pointer input signal from CD DSP.
i
I RAM Over Flow input signal of CD DSP.
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