Pioneer PDP-4271HD Service Manual page 195

5
Pin Function
2.5 Clock generator terminal
Acronyms Terminal I/O
number
XI 55 I
XO 54 O
BCLK8 102 I/O
µ
2.6 Terminal for PD64031A and
Acronyms Terminal I/O
number
FCLK8 78 I/O
FCKQ 127 I/O
FOCP 128 I/O
2.7 Terminal for RGB input
Acronyms Terminal I/O
number
DFBI 130 I
DYSI 131 I
DYMI 134 I
DCGI 135 I
DCBI 136 I
DCRI 137 I
FCSI 129 I/O
5
6
Level Buffer type
PU/PD [kΩ]
Analog –
Analog –
LVTTL 6 mA
3-state
µ
PD64032 digital connection
Level Buffer type
PU/PD [kΩ]
LVTTL 6 mA
3-state
LVTTL 3 mA
3-state
LVTTL 3 mA
3-state
Level Buffer type
PU/PD [kΩ]
LVTTL –
LVTTL –
LVTTL –
LVTTL –
LVTTL –
LVTTL –
LVTTL 3 mA
3-state
PDP-4271HD
6
7
Functions
Reference clock input
Connect 24.576MHz crystal oscillator.
Reference clock output
Connect 24.576MHz crystal oscillator.
Subsequent stage line lock clock monitor input/output
It will become Hi-Z when BCK8OUT (SA1Fh, D5)=0.
Normally, set to BCK8OUT=0 and leave it open.
Functions
Front stage burst lock clock input/output
It will become Hi-Z when FCK8S[2:0] (SA21h, D6-D4)=000b.
Normally, set to FCK8S[2:0]=0 and leave it open.
Sampling clock output for µPD64031A and µPD64032
digital connection.
It will become Hi-Z when FCKQS[2:0] (SA21h, D2-D0)=000b.
Normally, set to FCKQS[2:0]=0 and leave it open.
Clamp pulse output for µPD64031A and µPD64032 digital
connection/timing output (VD) for digital RGB input.
It will become Hi-Z when FOCPS[2:0] (SA23h, D2-D0)=000b.
Normally, set to FOCPS[2:0]=0 and leave it open.
Functions
Fast Blanking signal input for analog RGB input.
YS signal input for digital RGB input.
YM signal input for digital RGB input.
Digital RGB/G signal input
Digital RGB/B signal input
Digital RGB/R signal input
Sync separation signal input/timing output (HD) for RGB input.
It will become Hi-Z when FCSIS[2:0] (SA22h, D2-D0)=000b.
Normally, set to FCSIS[2:0]=0 and leave it open.
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A
B
C
D
E
F
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