LG KM500 Service Manual page 18

3.2.6 Digital Core
3.2.6.1 Digital Interface Block Diagram
3.2.6.1 Control system and digital interface
The B6PLD is a RF transceiver IC for GSM900, DCS1800 and PCS1900 quad band cellular system,
and incorporates EDGE transceiver capability. The B6PLD has a digital interface connection to the
baseband processor. This interface complies with the digital interface specification DigRF standard
v112.
The digital interface consists of two separate interface connections; (1) the control interface, (2) the
data interface, and a system clock on/off control signal and a precise timing signal. These are
realized by eight signal lines in B6PLD(Look at Fig1.1 above)
-. The control interface is used to configure the B6PLD for RX and TX operation, transfers of control
data for several built-in circuits, and for triggering the events. The control interface comprise a bi-
directional 3-wire serial interface with the three signal lines CtrlData, CtrlEn and CtrlClk accessing
the control registers in B6PLD by transferring the control words.
-. The data interface is used to transfer transmit modulation symbols and receive IQ-sampling data.
The data interface comprises a single serial bus with the three signal lines RxTxData, RxTxEn and
SysClk. The SysClk is used for system clock to baseband.
-. The SsClkEn signal enables the SysClk output and powers the 26MHz oscillator on. When the
SysClkEn is negated, the SysClk is held low, and if the TEST1 pin is low by the default settings, the
logic power supply by typical 1.8 volts to the internal core logic circuits is also switched off.
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Only for training and service purposes
Fig. 1-1 Digital Interface Block Digram
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3. HW Circuit Description
LGE Internal Use Only