LG -P970 Service Manual page 81

3.12.2.10 General Purpose IO
The general-purpose interface combines six general purpose IO banks Each GPIO module provides 3 dedicated
general purpose pins with input and output capabilities thus, the general purpose interface supports up to 19
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(6X3) pins.
Device
L4-Wake-up
interconnect
L4-Per
interconnect
Interface clock
PRCM
Debounce clock
Wake-up
requests
Interrupt requests
IVA2.2 subsystem
interrupt
controller
Interrupt requests
MPU subsystem
interrupt
controller
Each channel in GPIOs has the following features:
• The GPIOi.GPIO_OE
• The output line level reflects the value written in the
4 (L4) interconnect.
• The input line can be fed to GPIO through an optional and configurable debounce cell. (The
debouncing time value is global for all ports of one GPIO module, so up to five different debouncing
time values are possible.)
• The input line value is sampled into the
interconnect.
• In active mode, the input line can be used through level and edge detectors to trigger synchronous
interrupts. The edge (rising, falling, or both) or the level (logical 0, logical 1, or both) used can be
configured.
• In idle mode, the input line can be used to activate the asynchronous wake-up request (on edge
detection: Rising edge, falling edge, or both).
The module provides an alternative to the atomic test and set operations for the following registers:
• GPIOi.GPIO_DATAOUT
LGE Internal Use Only
• GPIOi.GPIO_IRQENABLE1
• GPIOi.GPIO_IRQENABLE2
• GPIOi.GPIO_WAKEUPENABLE
TI Confidential — NDA Restrictions
Figure 25-1. General-Purpose interface overview
General-purpose interface
GPIO2_ICLK
GPIO2_DBCLK
GPIO2_WAKE
6
GPIO2_IVA2_IRQ
6
GPIO2_MPU_IRQ
6
other GPIO modules
(GPIO3 to GPIO6)
register controls the output capability for each pin.
GPIOi.GPIO_DATAIN
GPIO1
GPIO1_ICLK
GPIO1_DBCLK
GPIO1_MPU_IRQ
GPIO1_IVA2_IRQ
GPIO1_WAKE
GPIO6
GPIO5
GPIO4
GPIO3
GPIO 2
GPIO_[127]
BANDGAP
TSHUT
GPIO_33
TV_DETECT
GPIOi.GPIO_DATAOUT
register and can be read through the L4
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3. TECHNICAL BRIEF
General-Purpose Interface Overview
GPIO_[31:0]
gpio_[31:0]
GPIO_[191:188]
gpio_[191:188]
GPIO_[186:160]
_
gpio_[186:160]
GPIO_[159:128]
gpio_[159:128]
gpio_[127]
GPIO_[126:96]
gpio_[126:96]
GPIO_[95:64]
gpio_[95:64]
GPIO_[63:34]
gpio_[63:34]
DAC1
register through the level
Only for training and service purposes
gpif-001