LG -P970 Service Manual page 72

3.12.2.2 Memory
Micro processor unit has a 3 bit address port , allowing it to handle a 4 GB space divided into several regions.
The Memory map is composed of a memory space and dedicated space Interconnect of the devices and the main
modules and subsystems in the platform.
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MPU
subsystem
SMS:
memory
scheduler /
OCM OCM
rotation
RAM
ROM
SDRC:
memory
controller
Stacked memories
SWPU176A – October 2009
LGE Internal Use Only
TI Confidential — NDA Restrictions
Figure 2-1. interconnect overview
IVA2.2
SGX sDMA
subsystem
SDRAM
GPMC: general-
UART3, UART4, McBSP2, McBSP3, McBSP4,
purpose memory
WDT3, GPTIMER2, GPTIMER3,
controller
GPTIMER4,GPTIMER5, GPTIMER6,
GPTIMER7, GPTIMER8, GPTIMER9, GPIO2,
GPIO3, GPIO4, GPIO5, GPIO6
SDRAM
External and stacked memories
External peripherals ports
Display
Camera
subsystem
ISP HS-OTG
L4 L4 L4
L3 interconnect
L4 interconnect (peripheral)
SCM, CM, display SS, sDMA, USB TLL,
HS USB Host, I2C1, I2C2, I2C3, UART1,
UART2, McBSP1, McBSP5, GPTIMER10,
ICR, camera ISP, MODEM,
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3. TECHNICAL BRIEF
USB USB
D2D
HS-HOST
L4 L4
L4 interconnect (core)
GPTIMER11, Mailbox, McSPI1,
McSPI2, McSPI3, McSPI4,
MMC/SD/SDIO1, MMC/SD/SDIO2,
MMC/SD/SDIO3, HDQ/1-Wire,
HS USB OTG
INTC, SR1, SR2, MPU INTC
L4 interconnect
GPTIMER1, WDT2,
GPIO1, 32KTIMER
External peripherals ports
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Only for training and service purposes
Introduction
DAP
L4
L4 interconnect
(emulation)
Emulation, trace, and
debug modules
(wake-up)
memmap-001
Memory Mapping 203