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3. TECHNICAL BRIEF
Power On Reset Generator
The power-on reset signals (RESET1P8 and RESET2P8) are asserted based on the VCORE (if
VAPPCFG = 0), VMEM, VEXT, and VPLL regulators. RESET1P8 and RESET2P8 are low when reset
is enabled and high when reset is disabled.
When the outputs of all four regulators reach their corresponding threshold voltages, reset will be
disabled after a nominal reset period of 130ms.
The outputs of all four regulators must remain at or above their corresponding threshold voltages for
the duration of the reset period for reset to be disabled (pulled high).
The nominal 130ms reset period is restarted whenever all four regulators reach their threshold
voltages. The nominal reset period of 130ms can be extended by connecting an external capacitor to
CRST. This capacitor is charged using a small current when reset is enabled. Once the capacitor
reaches the threshold, reset is disabled.
Reset will be enabled immediately if any one of the four regulators falls below their corresponding
threshold voltages. In addition, reset will be enabled if VBAT falls below VRTC. The PWREN signal is
the logical AND of all the state controls that enable or disable many of the regulators on the chip. If the
regulators enabled by PWREN are disabled by PMT state controls described below then PWREN
must go low.
When PWREN goes low reset will be immediately enabled causing RESET1P8 and RESET2P8 to be
pulled low.
When reset is enabled, both RESET1P8 and RESET2P8 are actively pulled low. CRST is also actively
pulled low when reset is enabled.
VABB Regulator Enable/Disable Logic Operation
The VABB regulator powers many on-chip analog circuits on the ABB. The VCXOEN signal, the
VABBEn bit in the LDOControl1 Bit Positions ( Addr 0x35) register, and the AFCDACMode and
AFCDACOn bits in the AuxControl1 Bit Positions ( Addr 0x13) register all particpate in controlling the
VABB enable/disable.
When the ABB power management system transitions from Off state, DDLO state, UVLO state, or
Thermal Shutdown State to Power Key Activation, Charger Activation, USB Charger Activation, or
Active State VABB will be enabled. During these state transitions ABBEn = 0 and AFCDACMode = 0,
VRF is enabled.
Once the ABB power management system is in Power Key Activation, Charger Activation, USB
Charger Activation, Active-Standby or Active State the VABB regulator enable/disable is controlled by
the information written to the VABBEn and AFCDACMode register bits by system software.
LGE Internal Use Only
Copyright © 2009 LG Electronics. Inc. All right reserved.
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Only for training and service purposes
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