LG 882LE Service Manual page 39

Power Management Pins Description
Pin Pin # Type Description
Name
SCDT 8 Out
PDO 9 In
PD 2 In
Differential Signal Data Pins Description
Pin Name Pin # Type
RX0+ 90 Analog
RX0- 91 Analog
RX1+ 85 Analog
RX1- 86 Analog
RX2+ 80 Analog
RX2- 81 Analog
RXC+ 93 Analog
RXC- 94 Analog
EXT_RES 96 Analog Impedance Matching Control. Resistor value should be ten times the characteristic
Reserved Pin Description
Pin Name Pin # Type Description
RESERVED 99 In
Power and Ground Pins Description
Pin Name Pin #
VCC 6,38,67
GND 5,39,68
OVCC 18,29,43,57,78
OGND 19,28,45,58,76 Ground Output GND.
AVCC 82,84,88,95
AGND 79,83,87,89,92 Ground Analog GND.
PVCC 97
PGND 98
Sync Detect. A HIGH level is outputted when DE is actively toggling indicating that the
link is alive. A LOW level is outputted when DE is inactive, indicating the link is down.
Can be connected to PDO to power down the outputs when DE is not detected. The
SCDT output itself, however, remains in the active mode at all times.
Output Driver Power Down (active LOW). A HIGH level indicates normal operation. A
LOW level puts all the output drivers only (except SCDT and CTL1) into a high
impedance (tri-state) mode. A weak internal pull-down device brings each output to
ground. PDO is a sub-set of the PD description. The chip is not in power-down mode
with this pin. There is an internal pull-up resistor that defaults the chip to normal
operation if left unconnected. SCDT and CTL1 are not tri-stated by this pin.
Power Down (active LOW). A HIGH level indicates normal operation and a LOW level
indicates power down mode. During power down mode, all output buffers are disabled
and brought low, all analog logic is powered down, and all inputs are disabled.
Description
TMDS Low Voltage Differential Signal input data pairs.
TMDS Low Voltage Differential Signal input data pairs.
impedance of the cable. In the common case of 50Ω transmission line, an external
500Ω resistor must be connected between AVCC and this pin.
Must be tied HIGH for normal operation.
Type Description
Power Digital Core VCC, must be set to 3.3V.
Ground Digital Core GND.
Power Output VCC, must be set to 3.3V.
Power Analog VCC must be set to 3.3V.
Power PLL Analog VCC must be set to 3.3V.
Ground PLL Analog GND.
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