LG 882LE Service Manual page 38

Output Pins Description
Pin Pin #
Type
Name
See
QE23- Out
Sil161A
QE0
Pin
Diagram
See
QO23-
Out
Sil161A
QO0
Pin
Diagram
44
ODCK Out
46 Out
DE
Out
48
HSYNC
47 Out
VSYNC
40 Out
CTL1
41 Out
CTL2
42 Out
CTL3
Configuration Pins Description
Pin Name Pin # Type Description
OCK_INV 100 In
PIXS 4 In
DFO 1 In
STAG_OUT 7 In
ST 3 In
Description
Output Even Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode
and to the first 24-bit pixel data for 2-pixels/clock mode.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Signal Mapping application note (SiI/AN-0007) which tabulates the
relationship between the input data to the transmitter and output data from the
receiver.
A low level on PD or PDO will put the output drivers into a high impedance(tri-state)
mode. A weak internal pull-down device brings each output to ground.
Output Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock
mode.
During 1-pixel/clock mode, these outputs are driven low.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Signal Mapping application note (SiI/AN-0007) which tabulates the
relationship between the input data to the transmitter and output data from the
receiver.
A low level on PD or PDO will put the output drivers into a high impedance(tri-state)
mode. A weak internal pull-down device brings each output to ground.
Output Data Clock. This output can be inverted using the OCK_INV pin. A low level
on PD or PDO will put the output driver into a high impedance (tri-state) mode. A
weak internal pull-down device brings the output to ground.
Output Data Enable. This signal qualifies the active data area. A HIGH level signifies
active display time and a LOW level signifies blanking time. This output signal is
synchronized with the output data. A low level on PD or PDO will put the output driver
into a high impedance (tri-state) mode. A weak internal pull-down device brings the
output to ground.
Horizontal Sync input control signal.
Vertical Sync input control signal.
General output control signal 1. This output is not powered down by PDO.
General output control signal 2.
General output control signal 3.
A low level on PD or PDO will put the output drivers (except CTL1 by PDO) into a
high impedance (tri-state) mode. A weak internal pull-down device brings each
output to ground.
ODCK Polarity. A LOW level selects normal ODCK output. A HIGH level selects
inverted ODCK output. All other output signals are not affected by this pin. They will
maintain the same timing no matter the setting of OCK_INV pin.
Pixel Select. A LOW level indicates one pixel (up to 24-bits) per clock mode using
QE[23:0]. A HIGH level indicates two pixels (up to 48-bits) per clock mode using
QE[23:0] for first pixel and QO[23:0] for second pixel.
Output Data Format. For all DVI applications, this pin should be tied LOW.
Staggered Output. A HIGH level selects normal simultaneous outputs on all odd and
even data lines. A LOW level selects staggered output drive. This function is only
available in 2-pixels per clock mode.
Output Drive. A HIGH level selects HIGH output drive strength. A LOW level selects
LOW output drive strength.
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