Aiwa 6ZG-1 Service Manual page 32

Pin No. Pin Name
95 CBLNK/FSC
96 CSYNC
97 XSGRST
98 CLK0O
99 DOUT
100 DATO
101 LRCO
102 BCKO
103 FSXI
104 VDD
105 VSS
106, 107 XTL2O, XTL2I
108 VDD
109 C2PO
110 LRCI
111 DATI
112 BCKI
113 DOIN
114 XHCS
115 XHDT
116 HRW
I/O
This terminal is used for the two signals of the composite blanking signal (CBLNK)
and the fsc signal. Use of this terminal is determined by the register setting. When
set to CBLNK, this terminal is used as output terminal when the internal sync
I/O
generator is used, and is used as input terminal when the internal sync generator is not
used. When set to fsc, the signal that is obtained by dividing-frequency of XTL0 is
output. The dividing ratio of either 1/8 or 1/16 can be selected.
Composite sync signal terminal. The composite sync signal is generated by frequency-
O
dividing the DCLK signal. This terminal cannot accept any inputs.
I Sync signal generator reset signal input. The internal generator is initialized by setting
this terminal to "L".
The clock signal that is obtained by frequency-dividing XTL0 is output from this
O
terminal. Dividing ratio of either 1, 1/2, 1/4 or 1/8 can be selected.
O Audio digital output terminal.
O Audio serial data output terminal to DAC.
O L/R clock output terminal to DAC.
O Bit clock output terminal to DAC.
Clock input for audio interface. Input the 256fs (11.2896 MHz), 384fs (16.9344
I
MHz), 512fs (22.5792 MHz) or (33.8688 MHz) etc., to this terminal.
— Power supply.
— GND.
Master clock terminal of the CD-ROM decoder and audio decoder. Either input the
clock signal to XTL2I or connect an external oscillator between XTL2I and XTL2O.
O/I
Recommended frequency is 45 MHz. This clock serves for internal circuit only, and is
not synchronized with the input and output signals.
— Power supply.
This is the terminal to input the C2 pointer from CD-DSP. It indicates that the DATI
I
input has an error.
This is the terminal to input the LR clock from CD-DSP. It indicates if it is L channel
I
or R channel.
I This is the terminal to input the serial data from CD-DSP.
This is the terminal to input the bit clock from CD-DSP. This is the clock to strobe the
I
DATI input.
I This is the terminal to input the digital data from CD-DSP.
I This is the terminal of the chip select input signal during register access.
This is the terminal to output the wait signal during register access. This terminal
outputs the unique wait signal that is generated or not generated by the register, during
I/O DRAM access when the host interface is in the parallel mode. The pull up resistor is
required since this terminal operates in the open drain configuration. Use the pull up
resistor in the serial mode operation too.
This terminal receives the R/W input signal when the host interface is in the parallel
I
mode. This terminal receives the serial clock input during the serial mode.
42
Description
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