Aiwa 6ZG-1 Service Manual page 30

IC, CXD1856R
Pin No. Pin Name
1 VSS
2, 3 XTL0O, XTL0I
4 VDD
5, 6, 119, 120 HA0-HA3
7-13, 16 HD0-HD7
14 VDD
15 VSS
17-21, 23, 24,
MA0-MA8
32, 33
22 VSS
25 CKEY
26 DTVLD
27-29 PIN27-PIN29
30 PIN30
31 VSS
34 XRAS
35 XMWE
36 XCAS2/MA9
37 XCAS0
38-43, 46-
MD0-MD15
55
44 VDD
I/O
— GND.
Video decoder master clock. Input the clock signal to the XTL0I or connect an
O/I external oscillator between XTL0I and XTL 0O. The recommend frequency is 27
MHz, 28.3636 MHz (NTSC 8fs) or 65.4686 MHz (PAL 8fs).
— Power supply.
This is the register address input terminal when the host interface is in the parallel
I mode. HA0 is the serial data input terminal in the serial mode. HA1 to HA3 must be
fixed to the "L" level during the serial mode.
This is the register data input/output terminal when the host interface is in the parallel
I/O mode. HA0 is the serial data output terminal in the serial mode. HD1 to HD7 must be
fixed the "L" level during the serial mode.
— Power supply.
— GND.
DRAM address signal output terminal. The DRAM address signal output terminal
O must be connected to the DRAM address terminal in the way that the terminal numbers
match each other.
— GND.
Chroma key signal terminal. This terminal goes to "L" while outputting the color that
O
is specified as the key color. Set this terminal to OPEN when it is not used.
Video data identification signal terminal. This terminal goes to "H" outputting the
O picture of the frame memory. This terminal goes to "L" while outputting the border
color or during blanking. Set this terminal to OPEN when it is not used.
— Not used.
— GND.
— GND.
Low address strobe signal output terminal. Connect this terminal to the DRAM RAS
O
signal terminal.
DRAM write enable signal output terminal. Connect this terminal to the DRAM WE
O
signal terminal.
Use this terminal when 8-Mbit DRAM is connected. Connect this terminal to the
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DRAM CAS signal terminal of the upper words (256K to 512K-1) side when the
O DRAM system consists of the two DRAMs * 256 * 16 bits (upper bite and lower bite
are common). Connect this terminal to the MA9 terminal (common to the two
DRAMs) when DRAM system consists of the two DRAMs * 512 Kw * 8 bits.
This is the DRAM column address strobe signal output. Connect this terminal to the
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DRAM CAS signal terminal of the lower words (0 to 256 K-1) side when DRAM
O system consists of the two DRAMs * 256 Kw * 16 bits (upper bite and lower bite are
common). Connect this terminal commonly to the DRAM CAS signal terminal in all
connections other than the above described connection.
DRAM data signal input/output terminal. These terminals must be connected to the
I/O
DRAM data terminals in the way that the terminal numbers match each other.
— Power supply.
40
Description
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