DSP 56301 Expansion Port Memory Map (AA0 chip select, 96K/88.2K mode 3)
Chip Select
AA0
AA0
AA0
AA0
AA0
AA0
AA0
AA0
DSP 56301 ESSI Ports
The DSP56301 has two Enhanced Synchronous Serial Interface (ESSI) ports which are used to send I2S
format serial digital data to the D/A converters and the MP-100 daughterboard and to receive I2S data from
the A/D converters. The ESSI ports are set up as shown in the following two tables:
DSP 56301 ESSI Port C Register
Port Bit Number
Signal Name
0
SCOPE_TRIG
1
DA_CH56
2
ESSI0_SYNC
3
ESSI0_CLK
4
AD_CH12
5
DA_CH12
DSP 56301 ESSI Port D Register
Port Bit Number
Signal Name
0
1
DA_CH78
2
ESSI1_SYNC
3
ESSI1_CLK
4
AD_CH34
5
DA_CH34
XCS10 FPGA (schematic sheet 2.)
The XCS10 Field Programmable Gate Array (FPGA) is a static RAM-based logic device that is used on the
Core2 to implement ADAT digital I/O and S/PDIF I/O. It also contains logic that interfaces to the serial
control ports of the input level control I.C.s, counters for the phase-locked loop, an I2S receiver interface
from the MP-100 daughterboard, and DMA control logic for moving samples between the DSP56301 and
the FPGA.
This device is programmed with one of several programs that are chosen by the user, depending on the I/O
configuration that is selected through the Lexicon Control Panel which runs on the host computer. The
FPGA may be programmed at any time by the DSP56301 to accommodate different I/O configurations.
Also shown on schematic sheet 2 are the crystal oscillators (Y2, Y3, and U28) which are used to generate
the on-board sample clocks.
Address
$100015-100017
$100012-100014
$10000F-100011
$10000C-10000E
$100009-10000B
$100006-100008
$100003-100005
$100000-100002
(for development only)
DAC channels 5 & 6
ESSI port 0 frame sync
Shift clock for ESSI 0 port
ADC channels 1 & 2
DAC channels 1 & 2
LEX_DIN
Reverb daughterboard I2S signal
DAC channels 7 & 8
ESSI port 1 frame sync
Shift clock for ESSI 1 port
ADC channels 3 & 4
DAC channels 3 & 4
ADAT Channel 8 (DMA only)
ADAT Channel 7 (DMA only)
ADAT Channel 6 (DMA only)
ADAT Channel 5 (DMA only)
ADAT Channel 4 (DMA only)
ADAT Channel 3 (DMA only)
ADAT Channel 2 (DMA only)
ADAT Channel 1 (DMA only)
Function
Function
Resource
In/Out
Active State
Output
Output
Input
high
Input
Input
Output
In/Out
Active State
Output
-
Output
-
Input
high
Input
-
Input
-
Output
-
Lexicon
-
-
-
-
-
6-5
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