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CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
SCL
SDA
1
1
1
1
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
SCL
t
SU:STA
SDA IN
SDA OUT
START
CONDITION
Figure 2. Start/Stop Timing
0
1
0
A
A
2
0
1
0
A
A
2
0
1
0
A
a
2
0
1
0
a
a
10
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
1
ACK DELAY (v t
Figure 4. Acknowledge Timing
t
t
F
HIGH
t
LOW
t
HD:DAT
t
HD:SDA
t
AA
Figure 5. Bus Timing
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A
R/W
CAT24C01 and CAT24C02
1
0
a
R/W
CAT24C04
1
8
a
R/W
CAT24C08
9
8
a
R/W
CAT24C16
9
8
8
9
)
AA
t
R
t
LOW
t
SU:DAT
t
DH
5
STOP
CONDITION
BUS RELEASE DELAY
(RECEIVER)
ACK SETUP (w t
)
SU:DAT
t
SU:STO
t
BUF
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