Pioneer VSX-321-K-P Service Manual page 35

5
• Pin Function
No. Name
1 ERROR/INT0
2
NPCM/INT1
3 MPIO_A0
4 MPIO_A1
5 MPIO_A2
6 MPIO_A3
7 MPIO_C0
8 MPIO_C1
9 MPIO_C2
10 MPIO_C3
11 MPIO_B0
12 MPIO_B1
13 MPIO_B2
14 MPIO_B3
15 MPO0
16 MPO1
17 DOUT
18 LRCK
19 BCK
20 SCKO
DGND
21
22 DVDD
23 MDO/ADR0
24 MDI/SDA
25 MC/SCL
26
MS/ADR1
27 MODE
28 RXIN7/ADIN0
29 RXIN6/ALRCKI0
30 RXIN5/ABCKI0
31 RXIN4/ASCKI0
32 RXIN3
33 RXIN2
34 RST
35 RXIN1
36 VDDRX
37 RXIN0
38 GNDRX
39 XTI
40 XTO
41 AGND
42 VCC
43 FILT
44 VCOM
45 AGNDAD
46 VCCAD
47 VINL
48 VINR
(1) Schmitt trigger input
(2) Schmitt trigger input
(3) Open-drain configuration in I2C mode
(4) Onboard pull-down resistor (50 kΩ, typical)
(5) CMOS Schmitt trigger input
5
6
In/Out
O DIR Error detection output / Interrupt0 output
O DIR Non-PCM detection output / Interrupt1 output
I/O Multipurpose I/O, Group A(1)
I/O Multipurpose I/O, Group A(1)
I/O Multipurpose I/O, Group A(1)
I/O Multipurpose I/O, Group A(1)
I/O Multipurpose I/O, Group C(1)
I/O Multipurpose I/O, Group C(1)
I/O Multipurpose I/O, Group C(1)
I/O Multipurpose I/O, Group C(1)
I/O Multipurpose I/O, Group B(1)
I/O Multipurpose I/O, Group B(1)
I/O Multipurpose I/O, Group B(1)
I/O Multipurpose I/O, Group B(1)
O Multipurpose output 0
O Multipurpose output 1
O Main output port, serial digital audio data output
O Main output port, LR clock output
O Main output port, Bit clock output
O Main output port, System clock output
— Ground, for digital
— Power supply, 3.3 V (typ.), for digital
I/O Software control I/F, SPI data output / I2C slave address setting0(2)
I/O Software control I/F, SPI data input / I2C data input/output(2) (3)
I Software control I/F, SPI clock input / I2C clock input(2)
I Software control I/F, SPI chip select / I2C slave address setting1(2)
I Control mode setting, (see the Serial Control Mode section, Control Mode Pin Setting)
I Biphase signal, input 7 / AUXIN0, serial audio data input(2)
I Biphase signal, input 6 / AUXIN0, LR clock input(2)
I Biphase signal, input 5 / AUXIN0, bit clock input(2)
I Biphase signal, input 4 / AUXIN0, system clock input(2)
I Biphase signal, input 3(2)
I Biphase signal, input 2(2)
I Reset Input, active low(2) (4)
I Biphase signal, input 1, built-in coaxial amplifier
— Power supply, 3.3 V (typ.), for RXIN0 and RXIN1.
I Biphase signal, input 0, built-in coaxial amplifier
— Ground, for RXIN
I Oscillation circuit input for crystal resonator or external XTI clock source input(5)
O Oscillation circuit output for crystal resonator
— Ground, for PLL analog
— Power supply, 3.3 V (typ.), for PLL analog
O External PLL loop filter connection terminal; must connect recommended filter
O ADC common voltage output; must connect external decoupling capacitor
— Ground, for ADC analog
— Power supply, 5.0 V (typ.), for ADC analog
I ADC analog voltage input, left channel
I ADC analog voltage input, right channel
HTP-071
6
7
Description
7
8
A
B
C
D
E
F
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