Panasonic SA-PM27E Service Manual page 139

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63 FCLK - Crystal frame clock signal output (fCLK = 7.35 kHz, double = 14.7 kHz)
64 IPFLAG - Interpolation flag output ("H" : Interpolation)
65 FLAG - Flag output
66 CLVS - Spindle servo phase synchronizing signal output ("H" : CLV, "L" : rough servo)
67 CRC - Sub-code CRC checked output ("H' :OK, "L" :NG)
68 DEMPH - De-emphassis ON signal output ("H" :ON)
69 RESY - Frame re-synchronizing signal output
70 IOSEL I Mode Switching Terminal
71 /TEST I Test input
72 AVDD1 I Power supply input (for analog circuit)
73 OUTL O Left channel audio signal output
74 AVSS1 I GND
75 OUTR O Right channel audio signal output
76 RSEL I RF signal polarity assignment input (at "H" level, RSEL="H", at "L" level, RESL="L")
77 IOVOD I 5V supply input
78 PSEL I Test terminal (connected to Gnd)
79 MSEL I SMCK oscillating frequency designation input ("L":4.2336 MHz, "H":8.4672 MHz)
80 SSEL I SUBQ output mode select ("H":Q-code buffer mode)
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