Panasonic SA-PM27E Service Manual page 138

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file:///C|/Documents%20and%20Settings/Administrator/Plocha/PANASONIC%20SA-PM27E/s1802000000.htm
27
TRD
O
Tracking drive output
28
FOD
O
Focus drive output
29
VREF
I
D/A (drive) output (TVD, ECS, TRD, FOD, FBAL, TBAL) Reference voltage input
30
FBAL
O
Focus balance adjustment output
31
TBAL
O
Tracking balance adjustment output
32
FE
I
Focus error signal input (analog input)
33
TE
I
Tracking error signal input (analog input)
34
RFENV
I
RF envelope signal input
35
VDET
I
Vibration detection signal input ("H" :detection)
36
OFT
I
Off-track signal input ("H" : off track)
37
TRCRS
I
Track cross signal input
38
/RFDET
I
RF detection signal input ("L" : detection)
39
BDO
I
Dropout signal input ("H" : Dropout)
40
LDON
O
Laser on signal output ("H" : ON)
41
PLLF2
I/O N.C.
42
DSLF2
O
Tracking Offset alignment output/DSL Balance Output (DA Output)
43
WVEL
O
N.C.
44
ARF
I
RF signal input
45
IREF
I
Reference current input
46
DRF
I
DSL bias terminal (Not used, open)
47
DSLF
I/O DSL loop filter terminal
48
PLLF
I/O PLL loop filter terminal
49
VCOF
I/O VCO loop filter terminal
50
AVDD2
I
Power supply input (for analog circuit)
51
AVSS2
I
GND (for analog circuit)
52
EFM
-
EFM signal output
53
PCK
-
PLL extraction clock output (fPCK = 4.321 MHz during normal playback)
54
VCOF2
I/O VCO Loop filter for 33.8688 MHz conversation terminal for 16.9344 MHz crystal mode, must use other circuit
55
SUBC
O
Sub-code serial data output
56
SBCK
I
Clock input for sub-code serial data
57
VSS
I
GND
58
X1 IN
I
Crystal oscillating circuit input (f = 16.9344MHz)
59
X2 OUT
O
Crystal oscillating circuit input (f = 16.9344 MHz)
60
VDD
I
Power supply input (for oscillating circuit)
61
BYTCK
-
Byte clock output
62
/CLDCK
-
Sub-code frame clock signal output (fCLDCK = 7.35 kHz during normal playback)
file:///C|/Documents%20and%20Settings/Administrator/Plocha/PANASONIC%20SA-PM27E/s1802000000.htm (2 of 3) [14.6.2003 18:48:01]

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