Sony HCD-GZR9D Service Manual page 88

HCD-GZR7D/GZR8D/GZR9D
Pin No. Pin Name
56 to 62 HA2 to HA8
63, 64 HA18, HA19
65 DVDD3
66 XWR
67 to 74 HA16 to HA9
75 HA20
76 XROMCS
77 HA1
78 XRD
79, 80 HD0, HD1
81 DVSS
82 to 86 HD2 to HD6
87 HA21
88 RESERVED
89 HD7
90 DVSS
91 HA17
92 HA0
93 DVDD18
94 FWD
95 REV
96 DVDD3
97 IFSDO
98 IFCK
99 xIFCS
100 IFSDI
101 SCL
102 SDA
103 CKSW
104 OCSW
105 RXD
106 TXD
107 ICE
108 xSYSRST
109 RESERVED
110 xIFBSY
111 DQM0
112 EEWP
113 to 117 RD7 to RD3
118 DVDD3
119 to 121 RD2 to RD0
122 to 129 RD15 to RD8
130 TSD_M
131 DVDD3
132 DQM1
133 _RWE
134 _CAS
135 _RAS
136 _RCS
137, 138 BA0, BA1
139 RA10
140, 141 RA0, RA1
142 DVDD18
143, 144 RA2, RA3
145 DVDD3
146 DRCLK
88
I/O
O Host address output bit 2 to 8
O Host address output bit 18, 19
— Power supply pin (+3.3 V) for internal digital circuitry
O Write enable output (active Low)
O Host address output bit 16 to 9
O Host address output bit 20
O Chip select output (active Low)
O Host address output bit 1
O Read enable output (active Low)
O Host data output bit 0, 1
— Ground pin for internal digital circuitry
O Host data output bit 2 to 6
O Host address output bit 21
O Not used. (Open)
O Host data output bit 7
— Ground pin for internal digital circuitry
O Host address output bit 17
O Host address output bit 0
— Power supply pin (+1.8 V) for internal digital circuitry
O Forward signal output for loading motor driver (Not used in this set)
O Reserve signal output for loading motor driver (Not used in this set)
— Power supply pin (+3.3 V) for internal digital circuitry
O External CPU serial data output (H/W method)
O External CPU serial clock output (H/W method)
O External CPU serial chip select output (active Low, H/W method)
I External CPU serial data input (H/W method)
O I2C clock output for EEPROM
O I2C data output for EEPROM
I Chucking switch detection input (Not used in this set)
I Open/close switch detection input (Not used in this set)
I Hardwired RS232C RXD input
O Hardwired RS232C TXD output
I ICE mode enable input (Not used in this set)
I MT1389 reset input (active Low)
I Not used. (Open)
I External CPU ready/busy interrupt signal input (L: ready, H: busy)
O Mask for DRAM output byte 0
O EEPROM write protect control output (L: write allowed)
O DRAM data output bit 7 to 3
— Power supply pin (+3.3 V) for internal digital circuitry
O DRAM data output bit 2 to 0
O DRAM data output bit 15 to 8
I Thermal shutdown monitor input
— Power supply pin (+3.3 V) for internal digital circuitry
O Mask for DRAM output byte 1
O DRAM write enable output
O DRAM column address strobe output
O DRAM row address strobe output
O DRAM chip select output
O DRAM bank address output 0, 1
O DRAM address output bit 10
O DRAM address output bit 0, 1
— Power supply pin (+1.8 V) for internal digital circuitry
O DRAM address output bit 2, 3
— Power supply pin (+3.3 V) for internal digital circuitry
O DRAM clock output
Description