Harman Kardon BDP 1/120 Service Manual page 48

Main Board Electric Diagram: BOOT STRAP OPTIONS & BCM7440B
Boot Strap Options
+3V3
1
1: Invert upper bits of EBI address
0
strap_ebi_invert_addr
0: Do not invert EBI address
1: External NAND FLASH present
1 strap_nand_flash
0: External NOR FLASH present
1: High-active interrupt
0 strap_NMI_polarity
0: Low-active interrupt
1: Swap CS_0 and CS_1 signals
0
strap_ebi_cs_swap
0: No swap
0
strap_reset_ext_mode
DEPOP
0 strap_test_debug_en_1
0 strap_test_debug_en_0 DEPOP
3: DDR2 Controller Manual Initialization
1 100MW
strap_ddr2_0_size_1
2: DDR2 bank 0 size = 256/512 MB
1 strap_ddr2_0_size_0 1: DDR2 bank 0 size = 128 MB
0: DDR2 bank 0 size = 64 MB 100MW
3: DDR2 Controller Manual Initialization
strap_ddr2_1_size_1
1
2: DDR2 bank 0 size = 256/512 MB
1 1: DDR2 bank 0 size = 128 MB 100MW
strap_ddr2_1_size_0
0: DDR2 bank 0 size = 64 MB
1 3: DDR2 Banks = 400/800 MHZ
strap_ddr2_mhz_1
2: DDR2 Banks = 333/667 MHZ
100MW
1: DDR2 Banks = 266/533 MHZ
1 strap_ddr2_mhz_0
0: DDR2 Banks = 200/400 MHZ
0 1: SPI slave port configured 100MW
strap_spi_slave_enable
0: BSC slave port configured int Fix.
1: Boot Flash = 16 bits
0 strap_ebi_boot_memory
0: Boot Flash = 8 bits
100MW
1: System is big endian
0 strap_system_big_endian
0: System is little endian
100MW
0 1: PCI in client (slave) mode
strap_pci_client
0: PCI in bridge (master) mode
1: PCI memwin 1 enable
0 strap_pci_memwin1_en
0: PCI memwin 1 disable
1: PCI memwin 2 enable DEPOP
0 strap_pci_memwin2_en
0: PCI memwin 2 disable
100MW
3: 256 MByte window
0
strap_pci_memwin_size_1
2: 128 MByte window
0 1: 64 MByte window
strap_pci_memwin_size_0
0: 32 MByte window
1 strap_33_27_MHZ_clock 1: 33 MHz clock output
0: 27 MHz clock output
0
strap_reset_outb_def_value
0
strap_xtal_adj3 Adjust the 54MHz oscillator bias current
0 strap_xtal_adj2
0
strap_xtal_adj1
0 strap_xtal_adj0
0
strap_ebi_rom_size1
3: NOR: 4 MBytes NAND: Disable ECC
0 2: NOR: 8 MBytes NAND: Disable ECC
strap_ebi_rom_size0
1: NOR: 16 MBytes NAND: Ebable ECC
0: NOR 64 MBytes NAND: Ebable ECC
1
100MW
1
100MW
1
100MW
1
100MW
1
100MW
Boot strap option --> Design notes and Layout Guidelines:
1- Note these configuration resistors do not need to be close to the BCM7440. So, place them at the destination of the trace.
It will clear the BCM7440 area and help the chip layout.
harman/kardon
BOOTSTRAP
(CLUSTER)
R67
1.5K
1 2
100MW 1%
strap_ebi_invert_addr
R59 EBI_~RD
EBI_~RD
4.64K 1%
2
strap_nand_flash
100MW EBI_~WE1
EBI_~WE1
R66 1.5K
1 2
100MW 1% strap_NMI_polarity
E BI_~TS
EBI_~TS
R65 1.5K
1 2
100MW 1% strap_ebi_cs_swap
EBI_~DS
EBI_~DS
R514 1.5K
1 2
R518
100MW 1% strap_reset_ext_mode
4.64K 1% DVO_D0
100MW DVO_D0
R520 1.5K
1 2 1 2
100MW 1% strap_test_debug_en_1
DVO_D2
DVO_D2
R516 4.64K
R515 1.5K
1 2 1 2
1% 100MW 1% strap_test_debug_en_0
DVO_D1
R519 DVO_D1
4.64K
1 2
1% strap_ddr2_0_size_1
DVO_D4
DVO_D4
R517
4.64K
1 2
1% strap_ddr2_0_size_0
DVO_D3
R525 DVO_D3
4.64K
1 2
1% strap_ddr2_1_size_1
DVO_D6
R523
DVO_D6
4.64K
1 2
1% strap_ddr2_1_size_0
DVO_D5
R521 DVO_D5
4.64K
1 2
1% strap_ddr2_mhz_1
DVO_CLK_P
R524 DVO_CLK_P
R522
4.64K
DEPOP
1 2 1 2
1% strap_ddr2_mhz_0
100MW 1%
1.5K
DVO_D7
DVO_D7
R32
4.64K
R541 1.5K
1 2 1 2
1% 100MW 1%
strap_ebi_boot_memory
I2S_0_CLOCK
R34 1.5K
1 2
100MW 1% strap_system_big_endian
I2S_0_LR
R30 1.5K
1 2
100MW 1% strap_pci_client
I2S_0_DATA0
R36
1.5K
1 2
100MW 1% strap_pci_memwin1_en
I2S_0_DATA1
R38
1.5K
1 2
100MW 1% strap_pci_memwin2_en
I2S_0_DATA2
R29 1.5K
1 2
100MW 1% strap_pci_memwin_size_0
R40 1.5K
1 2
100MW 1% strap_pci_memwin_size_1
I2S_S_DATA
R64
strap_33_27_MHZ_clock
4.64K
EBI_~WE0
2
EBI_~WE0
1%
R62 1.5K
1 2
100MW 1% strap_reset_outb_def_value
EBI_R~W
R60
strap_xtal_adj3
4.64K
2 EBI_A25
1%
strap_xtal_adj2
R28 1.5K
1 2
USB1_PWRON
100MW 1%
USB1_PWRON
R529
strap_xtal_adj1
4.64K
2 USB0_PWRON
USB0_PWRON
1% R39 1.5K
1 2
100MW 1% strap_xtal_adj0
AUD0_SPDIF
R63
strap_ebi_rom_size1
4.64K
EBI_~TSIZE1
2
EBI_~TSIZE1
1%
R61
strap_ebi_rom_size0
4.64K
E BI_~TSIZE0
2
1%
GND
+2V5_BCM7440
I2S_0_CLOCK
I2S_0_LR
I2S_0_DATA0
I2S_0_DATA1
I2S_0_DATA2
I2S_0_DATA3
I2 S_0_DATA3
I2S _S_DATA
EBI_R~W
EBI_A25
AUD0_SPDIF
E BI_~TSIZE0
48
BDP 1 / BDP 10 Service Manual
BCM7440 Power
SOC
(CLUSTER)
C646 C525 C611 C572 C43 C57 C541 C612
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
C613
C534
22UF
22UF
GND
2008.5.19
+2V5_BCM7440
C547 C581
C584 C42 C616
47UF 47UF
0.1UF 0.1UF 10UF/10V
GND
C641 C606 C65 C55 C617 C660 C636 C69 C51
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
C627 C56 C68 C67 C671 C50 C672 C66 C52
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
GND
C615
C583 C625 C621 C588 C585 C586 C34 C33
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
C36 C35 C623 C618 C620 C619
22UF 22UF 4.7UF 4.7UF 4.7UF 4.7UF
GND GND
Place 4.7uF directly
under chip.
+3V3
C647 C70 C614 C574 C610 C58 C648
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
GND
+1V8
C54 C629 C661 C628 C53
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
GND
+1V2
C587
0.1UF
GND