LG CED-8081B Service Manual page 56

IC301 (MB90F476) : MICOM
Block Diagram
Clock control
X0, X1 RSTX
5
X0, X1A
µDMA
Communication
SIN0
SOT0
SCK0
SIN1, 2
SOT1, 2
SCK1, 2
AVCC
AVRH.L
A/D converter
AVSS
ADTG
AN0 to 7
P00 to P07 (8) : Provided with input pull-up resistor setting register
P10 to P17 (8) : Provided with input pull-up resistor setting register
P40 to P47 (8) : Provided with open-drain setting register
P70 to P77 (6) : Provided with open-drain setting register
* NOTE: In the figure above, the I/O port shares the pins each internal functional block. When the pins are used
as internal module pins, they cannot be used as I/O port pins.
42
circuit
RAM
ROM
prescaler
2
UART
I/O expanded
serial
interface x2
channels
(10 bits)
8 8 8 8
P00 P10 P20 P30
P07 P17 P27 P37
CPU
2
F MC-16LX family Core
I/O port
8 8 8
P40 P50 P60
P47 P57 P67
Interrupt controller
8-/16-bit PPG
8-/16-bit UD counter
Chip select
I/O timer
16-bit input capture x2
16-bit output conveyer x6
16-bit free-run timer
16-bit reload timer
x2 channels
8
External interrupt
8 8 8 4
P70 P80 P90 PA0
P77 P87 P97 PA3
PPG0, 1
PPG2, 3
PPG4, 5
AIN0, 1
BIN0, 1
ZIN0, 1
CS0, 1, 2, 3
IN0, 1
OUT0, 1, 2,
3, 4, 5
TIN0
TOT0
IRQ0 to 7